ff.vhd

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fentclk is
	port(
		grst : in std_logic;
		fosc60m : in std_logic;
		refclk : out std_logic
		);
end fentclk;

architecture Behavioral of fentclk is
 	signal counter : integer range 0 to 4;
begin
	process(grst,fosc60m)
	begin
		if grst = '0' then
			counter <= 0;
			refclk <= '1';
		elsif fosc60m'event and fosc60m = '1' then
			counter <= counter + 1;
			if counter < 4 then
				refclk <= '1';
			else
				refclk <= '0';
			end if;
		end if;
	end process;

end Behavioral;