rece.schbak

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "spartan2e"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        SIGNAL rout(17:0)
        SIGNAL local_le
        SIGNAL led1
        SIGNAL line_le
        SIGNAL tpwdn
        SIGNAL rpwdn
        SIGNAL den
        SIGNAL ren
        SIGNAL fosc
        SIGNAL refclk
        SIGNAL lock
        SIGNAL XLXN_1
        SIGNAL XLXN_2
        SIGNAL rclk
        PORT Input rout(17:0)
        PORT Output local_le
        PORT Output led1
        PORT Output line_le
        PORT Output tpwdn
        PORT Output rpwdn
        PORT Output den
        PORT Output ren
        PORT Input fosc
        PORT Output refclk
        PORT Input lock
        PORT Input rclk
        BEGIN BLOCKDEF rece18
            TIMESTAMP 2008 10 13 2 6 36
            LINE N 64 32 0 32 
            LINE N 64 -224 0 -224 
            LINE N 64 -128 0 -128 
            RECTANGLE N 0 -44 64 -20 
            LINE N 64 -32 0 -32 
            LINE N 320 -416 384 -416 
            LINE N 320 -352 384 -352 
            LINE N 320 -288 384 -288 
            LINE N 320 -224 384 -224 
            LINE N 320 -160 384 -160 
            LINE N 320 -96 384 -96 
            LINE N 320 -32 384 -32 
            RECTANGLE N 64 -448 320 192 
        END BLOCKDEF
        BEGIN BLOCKDEF clk60
            TIMESTAMP 2008 9 30 0 52 28
            RECTANGLE N 64 -64 320 0 
            LINE N 64 -32 0 -32 
            LINE N 320 -32 384 -32 
        END BLOCKDEF
        BEGIN BLOCKDEF bufg
            TIMESTAMP 2001 2 2 12 51 12
            LINE N 64 -64 64 0 
            LINE N 128 -32 64 -64 
            LINE N 64 0 128 -32 
            LINE N 224 -32 128 -32 
            LINE N 0 -32 64 -32 
        END BLOCKDEF
        BEGIN BLOCKDEF ibuf
            TIMESTAMP 2001 2 2 12 53 1
            LINE N 64 0 64 -64 
            LINE N 128 -32 64 0 
            LINE N 64 -64 128 -32 
            LINE N 224 -32 128 -32 
            LINE N 0 -32 64 -32 
        END BLOCKDEF
        BEGIN BLOCK XLXI_6 clk60
            PIN fosc fosc
            PIN fosc60m refclk
        END BLOCK
        BEGIN BLOCK XLXI_8 bufg
            PIN I XLXN_2
            PIN O XLXN_1
        END BLOCK
        BEGIN BLOCK XLXI_9 rece18
            PIN fosc60m refclk
            PIN rclk XLXN_1
            PIN lock lock
            PIN rout(17:0) rout(17:0)
            PIN ren ren
            PIN den den
            PIN rpwdn rpwdn
            PIN tpwdn tpwdn
            PIN line_le line_le
            PIN led1 led1
            PIN local_le local_le
        END BLOCK
        BEGIN BLOCK XLXI_10 ibuf
            PIN I rclk
            PIN O XLXN_2
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        BEGIN BRANCH rout(17:0)
            WIRE 1200 1408 1216 1408
            WIRE 1216 1408 1264 1408
        END BRANCH
        BEGIN BRANCH local_le
            WIRE 1648 1408 1712 1408
            WIRE 1712 1408 1728 1408
        END BRANCH
        BEGIN BRANCH led1
            WIRE 1648 1344 1744 1344
            WIRE 1744 1344 1760 1344
        END BRANCH
        BEGIN BRANCH line_le
            WIRE 1648 1280 1744 1280
            WIRE 1744 1280 1760 1280
        END BRANCH
        BEGIN BRANCH tpwdn
            WIRE 1648 1216 1744 1216
            WIRE 1744 1216 1760 1216
        END BRANCH
        BEGIN BRANCH rpwdn
            WIRE 1648 1152 1664 1152
            WIRE 1664 1152 1680 1152
        END BRANCH
        IOMARKER 1680 1152 rpwdn R0 28
        BEGIN BRANCH den
            WIRE 1648 1088 1664 1088
            WIRE 1664 1088 1680 1088
        END BRANCH
        IOMARKER 1680 1088 den R0 28
        BEGIN BRANCH ren
            WIRE 1648 1024 1664 1024
            WIRE 1664 1024 1680 1024
        END BRANCH
        IOMARKER 1680 1024 ren R0 28
        IOMARKER 1200 1408 rout(17:0) R180 28
        IOMARKER 1728 1408 local_le R0 28
        IOMARKER 1760 1344 led1 R0 28
        IOMARKER 1760 1280 line_le R0 28
        IOMARKER 1760 1216 tpwdn R0 28
        BEGIN INSTANCE XLXI_6 1248 656 R0
        END INSTANCE
        BEGIN BRANCH fosc
            WIRE 1136 624 1248 624
        END BRANCH
        IOMARKER 1136 624 fosc R180 28
        IOMARKER 1856 624 refclk R0 28
        BEGIN BRANCH refclk
            WIRE 1056 720 1712 720
            WIRE 1056 720 1056 1376
            WIRE 1056 1376 1056 1472
            WIRE 1056 1472 1264 1472
            WIRE 1632 624 1712 624
            WIRE 1712 624 1712 720
            WIRE 1712 624 1856 624
        END BRANCH
        BEGIN BRANCH lock
            WIRE 1232 1312 1248 1312
            WIRE 1248 1312 1264 1312
        END BRANCH
        IOMARKER 1232 1312 lock R180 28
        INSTANCE XLXI_8 1024 1248 R0
        BEGIN BRANCH XLXN_1
            WIRE 1248 1216 1264 1216
        END BRANCH
        BEGIN BRANCH XLXN_2
            WIRE 992 1216 1024 1216
        END BRANCH
        BEGIN BRANCH rclk
            WIRE 672 1216 768 1216
        END BRANCH
        IOMARKER 672 1216 rclk R180 28
        BEGIN INSTANCE XLXI_9 1264 1440 R0
        END INSTANCE
        INSTANCE XLXI_10 768 1248 R0
    END SHEET
END SCHEMATIC