ctl.vhd

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ctl is
	port(
		grst : in std_logic;
		fosc120m : in std_logic;
		mode1 : in std_logic;
		mode2 : in std_logic;
		mode4 : in std_logic;
		rclk : in std_logic;
		lock : in std_logic;
		rout : in std_logic_vector(17 downto 0);
--		dout : out std_logic_vector(15 downto 0);
		wrclk : in std_logic;
		fifopaf : in std_logic;
		data : in std_logic_vector(11 downto 0);
		dataout : in std_logic_vector(11 downto 0);
		datain : out std_logic_vector(11 downto 0);
		refclk : out std_logic;
		tclk : out std_logic;
		sync : out std_logic;
		ren : out std_logic;
		den : out std_logic;
		tpwdn : out std_logic;
		rpwdn : out std_logic;
		local_le : out std_logic;
		line_le : out std_logic;
		wrfifo : out std_logic;
		rdfifo : out std_logic;
		addra : out std_logic_vector(10 downto 0);
		addrb : out std_logic_vector(10 downto 0);
		fifowr : out std_logic;
		fifowren : out std_logic;
		clk1 : out std_logic;
		clk2 : out std_logic;
		clk3 : out std_logic; 
		clk4 : out std_logic;
		flag2 : out std_logic;
		led1 : out std_logic;
		led2 : out std_logic;
		led3 : out std_logic;
		led4 : out std_logic;
		din : out std_logic_vector(17 downto 0)

		);
end ctl;

architecture Behavioral of ctl is
	signal offset : std_logic_vector(10 downto 0);
	signal f_rclk : std_logic;
	signal f_wrclk : std_logic;
	signal flag :std_logic;
	signal flag1 :std_logic;
	signal f_din : std_logic_vector(11 downto 0);
	signal addra_tmp : std_logic_vector(10 downto 0);
	signal addrb_tmp : std_logic_vector(10 downto 0);
	signal request_count : std_logic_vector(1 downto 0);
	signal wrclk_count : std_logic_vector(1 downto 0);
	signal sync_f : std_logic;
	signal f_data : std_logic_vector(11 downto 0);
	signal f_rout : std_logic_vector(17 downto 16);
	signal rdfifo_f : std_logic;
	signal counter : integer range 0 to 7;
begin
	ren <= '1';
	den <= '1';
	tpwdn <= '1';
	rpwdn <= '1';
	line_le <= '0';
	local_le <= '0';
	addra <= addra_tmp;
	addrb <= addrb_tmp;
	fifowren <= '0';
--	clk1 <= dataout(9);
--	clk2 <= f_data(9);
--	clk3 <= dataout(0);
--	clk4 <= f_data(0);
   flag2 <= '1' when rout(15 downto 0)= "0000000000000000"
	     else '0';

-----------------------------------120m fosc----------------------------------------
main : process(grst,fosc120m)
		variable w_cnt : integer range 0 to 15000000;
		variable w_st : integer range 0 to 8;
		variable r_st : integer range 0 to 6;
		variable frmcnt : std_logic_vector(15 downto 0);
		variable frmpos : integer range 0 to 2047;
		variable wrcount : integer range 0 to 31;

	begin
		if grst = '0' then
			tclk <= '1';
			sync <= '1';
			sync_f <= '1';
			w_st := 0;
			r_st := 0;
			frmcnt := (others => '0');
		elsif fosc120m'event and fosc120m = '1' then
		----------------download data	 -----------------------------------------------
			if mode4 = '0' then		 
				case w_st is
					when 0 =>
						rdfifo <= '1';
						addrb_tmp <= "00000000000";
						w_cnt := 0;
						w_st := 1;
						r_st := 0;
					when 1 =>
						tclk <= '1';
						w_st := 2;
						if w_cnt < 15000000 then    --------wait 1s
							w_cnt := w_cnt + 1;
							sync <= '1';
							sync_f <= '1';
						else	
							sync <= '0';
							sync_f <= '0';
						end if;
					when 2 =>
						w_st := 3;
						if sync_f = '0' then
							if offset = 0 then
								rdfifo_f <= '1';
								rdfifo <= '1';
							else
								rdfifo_f <= '0';
								rdfifo <= '0';	
							end if;
						else
							rdfifo_f <= '1';
						end if;
					when 3 =>
						rdfifo <= '1';
						w_st := 4;
					when 4 =>
						w_st := 5;
						if sync_f = '0' and rdfifo_f = '0' then
							f_din <= dataout;
						end if;
					when 5 =>
						tclk <= '0';
						w_st := 6;
						if sync_f = '0' then
							if rdfifo_f = '0' then
								din(17 downto 16) <= f_din(9 downto 8);
								din(15 downto 8) <= "00000000";
								din(7 downto 0)<= f_din(7 downto 0);
							else
								din <= "00" &"0101010101010101";	----ineffect data
							end if;
						end if;
					when 6 =>
						w_st := 7;
						if rdfifo_f = '0' then
							addrb_tmp <= addrb_tmp + 1;
						else
							addrb_tmp <= addrb_tmp;
						end if;
					when 7 =>
						w_st := 8;
					when 8 =>
						w_st := 1;
					when others =>
						w_st := 0;
				end case;
		------------------------------upload data -------------------------------------
--			else					 
--				case r_st is
--					when 0 =>
--						tclk <= '1';
--						fifowr <= '1';
--						wrcount := 0;
--						w_st := 0;
--						r_st := 1;
--					when 1 =>
--						if wrcount = 23 then
--						   fifowr <= '0';
--							wrcount := 0; 
--						   r_st := 2;
--                  else
--							wrcount := wrcount +1;
--						   r_st := 1;
--                  end if;
--						if lock = '0' then
--							r_st := 2;
--						else
--							r_st := 1;
--						end if;
--					when 2 =>
								
--						if f_rclk = '1' then  ----------调试时注意
--							r_st := 3;
--							fifowr <= '1';
--						else
--							r_st := 2;
--						end if;
--					when 3 =>						
--						if f_rclk = '0' then    ---------调试时注意
--							f_rout <= rout;
--							r_st := 4;
--						else
--							r_st := 3;
--						end if;
--					when 2 =>
--						if flag1 = '0' then
--						if rout(17 downto 16) = "10" then
--							if frmpos = 1206 then
--								dout <= X"EB93";
--								frmcnt := frmcnt + 1;
--							elsif frmpos = 1205 or frmpos = 1204 then
--								dout <= X"EB93";
--							elsif frmpos = 1203 then
--								dout <= frmcnt;
--							else
--								dout <= X"0001";
--							end if;
--							r_st := 3;
--					   else
--							r_st := 2;
--						end if;
--					when 3 =>
--						fifowr <= '0';
--						if frmpos = 1206 then
--							frmpos := 0;
--						else
--							frmpos := frmpos + 1;
--						end if;
--						r_st := 4;
--					when 4 =>
--					 	if wrcount = 21 then 
--						   fifowr <= '1';
--						   wrcount := 0;
--							r_st :=1;
--						else
--						   wrcount := wrcount + 1;
--							r_st := 4;
--						end if;						
--						r_st := 6;
--               when 6 =>
--						fifowr <= '1';
--						r_st := 2;
--					when others =>
--						r_st := 0;
--				end case;
			end if;
		end if;	
	end process main; 
	----------------------wr 2k fifo-------------------------	
	p1:process(grst,fosc120m)
		variable fifo_st : integer range 0 to 7;
	begin
		if grst = '0'then
			fifo_st := 0;
	     	addra_tmp <= "00000000000";
		elsif fosc120m'event and fosc120m = '0'then
			if mode4 = '0' then
				case fifo_st is
					when 0 =>
						wrfifo <= '1';
	     				addra_tmp <= "00000000000";
						fifo_st := 1;
					when 1 =>
						if f_wrclk = '0' then
							fifo_st := 2;
						else
							fifo_st := 1;
						end if;
					when 2 =>
						if f_wrclk = '1' then
							f_data <= data;
							fifo_st := 3;
						else
							fifo_st := 2;
						end if;
					when 3 =>
						if flag ='1' then
--						if f_data(11 downto 10) = "00" then							
							fifo_st := 4;
						else
							fifo_st := 1;
						end if;
					when 4 =>
					   datain <= f_data;						
						fifo_st := 5;
					when 5 =>
						wrfifo <= '0';						
						fifo_st := 6;
					when 6 =>
						wrfifo <= '1';
						fifo_st := 7;
               when 7 => 
						addra_tmp <= addra_tmp + 1;
						fifo_st := 1;
					when others =>
						fifo_st := 0;
				end case;
			else
				fifo_st := 0;
			end if;	
		end if;
	end process p1;
	 -----------------------address compare--------------------------
    p2: process(fosc120m)
    begin
    		if fosc120m'event and fosc120m = '0' then
			if	addra_tmp >= addrb_tmp then
				offset <= addra_tmp - addrb_tmp;
			else
				offset <= 2047 + addra_tmp - addrb_tmp;
			end if;
		end if;
	end process p2;
	--------------------------------------------rclk xiao dou----------------------------------
	p3: process(grst, fosc120m)
	begin
		if grst='0' then
			request_count<="00";
			f_rclk<='1';
		elsif fosc120m ' event and fosc120m='1' then
			if rclk='0' and request_count(1)='0' and f_rclk='1' then
				f_rclk<='1';
				request_count<=request_count+1;
			elsif rclk='0' and request_count(1)='1' and f_rclk='1' then
				f_rclk<='0';
				request_count<="00";
			elsif rclk='1' and request_count(1)='0' and f_rclk='0' then
				f_rclk<='0';
				request_count<=request_count+1;
			elsif rclk='1' and request_count(1)='1' and f_rclk='0' then
				f_rclk<='1';
				request_count<="00";
			else
				request_count<="00";
			end if;
		end if;
	end process p3;
	-----------------------------produce refclk------------------------------------
	p4 : process(grst,fosc120m)
	begin
		if grst = '0' then
			counter <= 0;
			refclk <= '1';
		elsif fosc120m'event and fosc120m = '1' then
			counter <= counter + 1;
			if counter < 3 then
				refclk <= '1';
			else
				refclk <= '0';
			end if;
		end if;
	end process p4;
  ----------------------------wrclk xiao dou---------------------------------------
	p5: process(grst, fosc120m)
	begin
		if grst='0' then
			wrclk_count<="00";
			f_wrclk<='1';
		elsif fosc120m ' event and fosc120m='1' then
			if wrclk='0' and wrclk_count(1)='0' and f_wrclk='1' then
				f_wrclk<='1';
				wrclk_count<=wrclk_count+1;
			elsif wrclk='0' and wrclk_count(1)='1' and f_wrclk='1' then
				f_wrclk<='0';
				wrclk_count<="00";
			elsif wrclk='1' and wrclk_count(1)='0' and f_wrclk='0' then
				f_wrclk<='0';
				wrclk_count<=wrclk_count+1;
			elsif wrclk='1' and wrclk_count(1)='1' and f_wrclk='0' then
				f_wrclk<='1';
				wrclk_count<="00";
			else
				wrclk_count<="00";
			end if;
		end if;
	end process p5;
--	flag <= '1' when rout(17 downto 16) = "10" else
--	'0';
   flag1 <= not rout(17) or rout(16);
	fifowr <= rclk or flag1;
   flag <= f_data(11) nor f_data(10);
	led1 <= fifopaf;
	led2 <= mode1;
	led3 <= mode2;
	led4 <= mode4;
end Behavioral;