rece18.vhi

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

-- VHDL Instantiation Created from source file rece18.vhd -- 10:15:19 10/13/2008
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT rece18
	PORT(
		fosc60m : IN std_logic;
		rclk : IN std_logic;
		lock : IN std_logic;
		rout : IN std_logic_vector(17 downto 0);          
		ren : OUT std_logic;
		den : OUT std_logic;
		rpwdn : OUT std_logic;
		tpwdn : OUT std_logic;
		line_le : OUT std_logic;
		led1 : OUT std_logic;
		local_le : OUT std_logic
		);
	END COMPONENT;

	Inst_rece18: rece18 PORT MAP(
		fosc60m => ,
		rclk => ,
		lock => ,
		rout => ,
		ren => ,
		den => ,
		rpwdn => ,
		tpwdn => ,
		line_le => ,
		led1 => ,
		local_le => 
	);