rece.vhi

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

-- Vhdl instantiation template created from schematic rece.sch - Tue Sep 30 08:54:39 2008
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module.
-- 2) To use this template to instantiate this component, cut-and-paste and then edit.
--

   COMPONENT rece
   PORT( fosc	:	IN	STD_LOGIC; 
          rclk	:	IN	STD_LOGIC; 
          lock	:	IN	STD_LOGIC; 
          rout	:	IN	STD_LOGIC_VECTOR (17 DOWNTO 0); 
          local_le	:	OUT	STD_LOGIC; 
          led1	:	OUT	STD_LOGIC; 
          line_le	:	OUT	STD_LOGIC; 
          tpwdn	:	OUT	STD_LOGIC; 
          rpwdn	:	OUT	STD_LOGIC; 
          den	:	OUT	STD_LOGIC; 
          ren	:	OUT	STD_LOGIC; 
          refclk	:	OUT	STD_LOGIC);
   END COMPONENT;

   UUT: rece PORT MAP(
		fosc => , 
		rclk => , 
		lock => , 
		rout => , 
		local_le => , 
		led1 => , 
		line_le => , 
		tpwdn => , 
		rpwdn => , 
		den => , 
		ren => , 
		refclk => 
   );