reportgen.log

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

Release 7.1i reportgen H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

B5A6955F24534CE::  Tue Sep 30 09:54:52 2008

D:/Xilinx/bin/nt/reportgen.exe -delay -intstyle ise -o rece rece.ncd 

Loading device for application Rf_Device from file '2s100e.nph' in environment
D:/Xilinx.
   "rece" is an NCD, version 3.1, device xc2s100e, package tq144, speed -6
ReportGen:LoadDesign: 'rece.ncd'
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)
Device speed data version:  "PRODUCTION 1.18 2005-01-22".

Generating Delay Report: rece.dly


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.804
   The MAXIMUM PIN DELAY IS:                               3.886
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.834

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         146          37          16           3           0           0


**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|         refclk_OBUF |      GCLKBUF1| No   |   29 |  0.133     |  0.491      |
+---------------------+--------------+------+------+------------+-------------+


Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

reportgen done!