rece18.syr

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: rece18.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "rece18.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "rece18"
Output Format                      : NGC
Target Device                      : xc2s100e-6-tq144

---- Source Options
Top Module Name                    : rece18
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : rece18.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/2222/rece18.vhd" in Library work.
Architecture behavioral of Entity rece18 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rece18> (Architecture <behavioral>).
Entity <rece18> analyzed. Unit <rece18> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <rece18>.
    Related source file is "D:/2222/rece18.vhd".
WARNING:Xst:647 - Input <fosc60m> is never used.
    Found 1-bit register for signal <led1>.
    Found 18-bit register for signal <dout>.
    Found 8-bit adder for signal <$n0000> created at line 81.
    Found 8-bit comparator equal for signal <$n0006> created at line 86.
    Found 8-bit register for signal <a>.
    Found 8-bit register for signal <b>.
    Found 18-bit register for signal <f_datain>.
    Summary:
	inferred  53 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <rece18> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 8-bit adder                       : 1
# Registers                        : 22
 1-bit register                    : 19
 18-bit register                   : 1
 8-bit register                    : 2
# Comparators                      : 1
 8-bit comparator equal            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Register <b_0> equivalent to <dout_0> has been removed
Register <b_1> equivalent to <dout_1> has been removed
Register <b_2> equivalent to <dout_2> has been removed
Register <b_3> equivalent to <dout_3> has been removed
Register <b_4> equivalent to <dout_4> has been removed
Register <b_5> equivalent to <dout_5> has been removed
Register <b_6> equivalent to <dout_6> has been removed
Register <b_7> equivalent to <dout_7> has been removed

Optimizing unit <rece18> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block rece18, actual ratio is 2.
FlipFlop dout_7 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_6 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_4 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : rece18.ngr
Top Level Output File Name         : rece18
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 46

Macro Statistics :
# Registers                        : 22
#      1-bit register              : 19
#      18-bit register             : 1
#      8-bit register              : 2
# Adders/Subtractors               : 1
#      8-bit adder                 : 1
# Comparators                      : 1
#      8-bit comparator equal      : 1

Cell Usage :
# BELS                             : 37
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 7
#      LUT2                        : 1
#      LUT4                        : 1
#      LUT4_L                      : 6
#      MUXCY                       : 11
#      VCC                         : 1
#      XORCY                       : 7
# FlipFlops/Latches                : 53
#      FDC_1                       : 18
#      FDE_1                       : 35
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 44
#      IBUF                        : 19
#      OBUF                        : 25
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100etq144-6 

 Number of Slices:                      38  out of   1200     3%  
 Number of Slice Flip Flops:            53  out of   2400     2%  
 Number of 4 input LUTs:                15  out of   2400     0%  
 Number of bonded IOBs:                 46  out of    102    45%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
rclk                               | BUFGP                  | 53    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.181ns (Maximum Frequency: 193.013MHz)
   Minimum input arrival time before clock: 8.277ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'rclk'
  Clock period: 5.181ns (frequency: 193.013MHz)
  Total number of paths / destination ports: 34 / 9
-------------------------------------------------------------------------
Delay:               5.181ns (Levels of Logic = 6)
  Source:            a_0 (FF)
  Destination:       led1 (FF)
  Source Clock:      rclk falling
  Destination Clock: rclk falling

  Data Path: a_0 to led1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            1   0.992   0.920  a_0 (a_0)
     LUT4_L:I0->LO         1   0.468   0.000  Eq_stagelut (N3)
     MUXCY:S->O            1   0.515   0.000  Eq_stagecy (Eq_stage_cyo)
     MUXCY:CI->O           1   0.058   0.000  Eq_stagecy_rn_0 (Eq_stage_cyo1)
     MUXCY:CI->O           1   0.058   0.000  Eq_stagecy_rn_1 (Eq_stage_cyo2)
     MUXCY:CI->O           1   0.058   0.920  Eq_stagecy_rn_2 (_n0006)
     LUT4_L:I0->LO         1   0.468   0.000  _n000237 (_n0002)
     FDE_1:D                   0.724          led1
    ----------------------------------------
    Total                      5.181ns (3.341ns logic, 1.840ns route)
                                       (64.5% logic, 35.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'rclk'
  Total number of paths / destination ports: 107 / 79
-------------------------------------------------------------------------
Offset:              8.277ns (Levels of Logic = 2)
  Source:            lock (PAD)
  Destination:       a_1 (FF)
  Destination Clock: rclk falling

  Data Path: lock to a_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            19   0.797   2.950  lock_IBUF (lock_IBUF)
     INV:I->O             35   0.468   3.375  led1_N01_INV_0 (led1_N0)
     FDE_1:CE                  0.687          led1
    ----------------------------------------
    Total                      8.277ns (1.952ns logic, 6.325ns route)
                                       (23.6% logic, 76.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'rclk'
  Total number of paths / destination ports: 19 / 19
-------------------------------------------------------------------------
Offset:              6.514ns (Levels of Logic = 1)
  Source:            led1 (FF)
  Destination:       led1 (PAD)
  Source Clock:      rclk falling

  Data Path: led1 to led1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            1   0.992   0.920  led1 (led1_OBUF)
     OBUF:I->O                 4.602          led1_OBUF (led1)
    ----------------------------------------
    Total                      6.514ns (5.594ns logic, 0.920ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
CPU : 5.86 / 12.34 s | Elapsed : 6.00 / 11.00 s
 
--> 

Total memory usage is 87612 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)