📄 fifo12bit_2k.vhf
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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1i
-- \ \ Application : sch2vhdl
-- / / Filename : fifo12bit_2k.vhf
-- /___/ /\ Timestamp : 10/13/2008 11:03:53
-- \ \ / \
-- \___\/\___\
--
--Command: D:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family spartan2e -flat -suppress -w fifo12bit_2k.sch fifo12bit_2k.vhf
--Design Name: fifo12bit_2k
--Device: spartan2e
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity fifo12bit_2k is
port ( adda : in std_logic_vector (10 downto 0);
addb : in std_logic_vector (10 downto 0);
datain : in std_logic_vector (11 downto 0);
fiford : in std_logic;
fifowr : in std_logic;
dataout : out std_logic_vector (11 downto 0));
end fifo12bit_2k;
architecture BEHAVIORAL of fifo12bit_2k is
attribute INIT_00 : string ;
attribute INIT_01 : string ;
attribute INIT_02 : string ;
attribute INIT_03 : string ;
attribute INIT_04 : string ;
attribute INIT_05 : string ;
attribute INIT_06 : string ;
attribute INIT_07 : string ;
attribute INIT_08 : string ;
attribute INIT_09 : string ;
attribute INIT_0A : string ;
attribute INIT_0B : string ;
attribute INIT_0C : string ;
attribute INIT_0D : string ;
attribute INIT_0E : string ;
attribute INIT_0F : string ;
attribute BOX_TYPE : string ;
signal XLXN_28 : std_logic_vector (1 downto 0);
signal XLXN_31 : std_logic_vector (1 downto 0);
signal XLXN_32 : std_logic_vector (1 downto 0);
signal XLXN_33 : std_logic_vector (1 downto 0);
signal XLXN_39 : std_logic_vector (1 downto 0);
signal XLXN_41 : std_logic_vector (1 downto 0);
signal XLXN_43 : std_logic_vector (1 downto 0);
signal XLXN_45 : std_logic_vector (1 downto 0);
signal XLXN_47 : std_logic_vector (1 downto 0);
signal XLXN_49 : std_logic_vector (1 downto 0);
signal XLXN_63 : std_logic_vector (1 downto 0);
signal XLXN_74 : std_logic_vector (1 downto 0);
signal XLXN_83 : std_logic;
signal XLXN_84 : std_logic;
signal XLXN_87 : std_logic;
signal XLXN_88 : std_logic;
signal XLXN_89 : std_logic;
component data_part
port ( datain : in std_logic_vector (11 downto 0);
dataout1 : out std_logic_vector (1 downto 0);
dataout2 : out std_logic_vector (1 downto 0);
dataout3 : out std_logic_vector (1 downto 0);
dataout4 : out std_logic_vector (1 downto 0);
dataout5 : out std_logic_vector (1 downto 0);
dataout6 : out std_logic_vector (1 downto 0));
end component;
component data_unite
port ( datain1 : in std_logic_vector (1 downto 0);
datain2 : in std_logic_vector (1 downto 0);
datain3 : in std_logic_vector (1 downto 0);
datain4 : in std_logic_vector (1 downto 0);
datain5 : in std_logic_vector (1 downto 0);
datain6 : in std_logic_vector (1 downto 0);
dataout : out std_logic_vector (11 downto 0));
end component;
component RAMB4_S2_S2
-- synopsys translate_off
generic( INIT_00 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port ( ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
attribute INIT_00 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of RAMB4_S2_S2 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute BOX_TYPE of RAMB4_S2_S2 : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
begin
XLXI_1 : data_part
port map (datain(11 downto 0)=>datain(11 downto 0),
dataout1(1 downto 0)=>XLXN_74(1 downto 0),
dataout2(1 downto 0)=>XLXN_28(1 downto 0),
dataout3(1 downto 0)=>XLXN_63(1 downto 0),
dataout4(1 downto 0)=>XLXN_31(1 downto 0),
dataout5(1 downto 0)=>XLXN_32(1 downto 0),
dataout6(1 downto 0)=>XLXN_33(1 downto 0));
XLXI_2 : data_unite
port map (datain1(1 downto 0)=>XLXN_39(1 downto 0),
datain2(1 downto 0)=>XLXN_41(1 downto 0),
datain3(1 downto 0)=>XLXN_43(1 downto 0),
datain4(1 downto 0)=>XLXN_45(1 downto 0),
datain5(1 downto 0)=>XLXN_47(1 downto 0),
datain6(1 downto 0)=>XLXN_49(1 downto 0),
dataout(11 downto 0)=>dataout(11 downto 0));
XLXI_3 : RAMB4_S2_S2
port map (ADDRA(10 downto 0)=>adda(10 downto 0),
ADDRB(10 downto 0)=>addb(10 downto 0),
CLKA=>fifowr,
CLKB=>fiford,
DIA(1 downto 0)=>XLXN_74(1 downto 0),
DIB(1 downto 0)=>XLXN_74(1 downto 0),
ENA=>XLXN_83,
ENB=>XLXN_88,
RSTA=>XLXN_84,
RSTB=>XLXN_89,
WEA=>XLXN_83,
WEB=>XLXN_87,
DOA=>open,
DOB(1 downto 0)=>XLXN_39(1 downto 0));
XLXI_4 : RAMB4_S2_S2
port map (ADDRA(10 downto 0)=>adda(10 downto 0),
ADDRB(10 downto 0)=>addb(10 downto 0),
CLKA=>fifowr,
CLKB=>fiford,
DIA(1 downto 0)=>XLXN_63(1 downto 0),
DIB(1 downto 0)=>XLXN_63(1 downto 0),
ENA=>XLXN_83,
ENB=>XLXN_88,
RSTA=>XLXN_84,
RSTB=>XLXN_89,
WEA=>XLXN_83,
WEB=>XLXN_87,
DOA=>open,
DOB(1 downto 0)=>XLXN_43(1 downto 0));
XLXI_5 : RAMB4_S2_S2
port map (ADDRA(10 downto 0)=>adda(10 downto 0),
ADDRB(10 downto 0)=>addb(10 downto 0),
CLKA=>fifowr,
CLKB=>fiford,
DIA(1 downto 0)=>XLXN_31(1 downto 0),
DIB(1 downto 0)=>XLXN_31(1 downto 0),
ENA=>XLXN_83,
ENB=>XLXN_88,
RSTA=>XLXN_84,
RSTB=>XLXN_89,
WEA=>XLXN_83,
WEB=>XLXN_87,
DOA=>open,
DOB(1 downto 0)=>XLXN_45(1 downto 0));
XLXI_6 : RAMB4_S2_S2
port map (ADDRA(10 downto 0)=>adda(10 downto 0),
ADDRB(10 downto 0)=>addb(10 downto 0),
CLKA=>fifowr,
CLKB=>fiford,
DIA(1 downto 0)=>XLXN_28(1 downto 0),
DIB(1 downto 0)=>XLXN_28(1 downto 0),
ENA=>XLXN_83,
ENB=>XLXN_88,
RSTA=>XLXN_84,
RSTB=>XLXN_89,
WEA=>XLXN_83,
WEB=>XLXN_87,
DOA=>open,
DOB(1 downto 0)=>XLXN_41(1 downto 0));
XLXI_7 : RAMB4_S2_S2
port map (ADDRA(10 downto 0)=>adda(10 downto 0),
ADDRB(10 downto 0)=>addb(10 downto 0),
CLKA=>fifowr,
CLKB=>fiford,
DIA(1 downto 0)=>XLXN_32(1 downto 0),
DIB(1 downto 0)=>XLXN_32(1 downto 0),
ENA=>XLXN_83,
ENB=>XLXN_88,
RSTA=>XLXN_84,
RSTB=>XLXN_89,
WEA=>XLXN_83,
WEB=>XLXN_87,
DOA=>open,
DOB(1 downto 0)=>XLXN_47(1 downto 0));
XLXI_8 : RAMB4_S2_S2
port map (ADDRA(10 downto 0)=>adda(10 downto 0),
ADDRB(10 downto 0)=>addb(10 downto 0),
CLKA=>fifowr,
CLKB=>fiford,
DIA(1 downto 0)=>XLXN_33(1 downto 0),
DIB(1 downto 0)=>XLXN_33(1 downto 0),
ENA=>XLXN_83,
ENB=>XLXN_88,
RSTA=>XLXN_84,
RSTB=>XLXN_89,
WEA=>XLXN_83,
WEB=>XLXN_87,
DOA=>open,
DOB(1 downto 0)=>XLXN_49(1 downto 0));
XLXI_25 : VCC
port map (P=>XLXN_83);
XLXI_27 : VCC
port map (P=>XLXN_88);
XLXI_29 : GND
port map (G=>XLXN_87);
XLXI_30 : GND
port map (G=>XLXN_89);
XLXI_32 : GND
port map (G=>XLXN_84);
end BEHAVIORAL;
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