data_part.twr

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise d:\2222\2222.ise -intstyle ise -e 3 -l 3 -s 6
-xml data_part data_part.ncd -o data_part.twr data_part.pcf


Design file:              data_part.ncd
Physical constraint file: data_part.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
datain<0>      |dataout1<0>    |    5.916|
datain<10>     |dataout6<0>    |    5.876|
datain<11>     |dataout6<1>    |    5.995|
datain<1>      |dataout1<1>    |    5.876|
datain<2>      |dataout2<0>    |    6.023|
datain<3>      |dataout2<1>    |    5.989|
datain<4>      |dataout3<0>    |    6.049|
datain<5>      |dataout3<1>    |    5.989|
datain<6>      |dataout4<0>    |    5.848|
datain<7>      |dataout4<1>    |    6.310|
datain<8>      |dataout5<0>    |    5.916|
datain<9>      |dataout5<1>    |    6.733|
---------------+---------------+---------+

Analysis completed Mon Oct 13 10:57:38 2008
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Peak Memory Usage: 69 MB