clk60.schbak

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "spartan2e"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        SIGNAL XLXN_1
        SIGNAL XLXN_2
        SIGNAL fosc60m
        SIGNAL XLXN_4
        SIGNAL fosc
        PORT Output fosc60m
        PORT Input fosc
        BEGIN BLOCKDEF clkdll
            TIMESTAMP 2001 5 5 15 22 1
            LINE N 384 -512 320 -512 
            LINE N 384 -448 320 -448 
            LINE N 384 -384 320 -384 
            LINE N 0 -448 64 -448 
            LINE N 0 -512 64 -512 
            LINE N 0 -128 64 -128 
            LINE N 384 -128 320 -128 
            LINE N 384 -192 320 -192 
            LINE N 384 -256 320 -256 
            LINE N 384 -320 320 -320 
            LINE N 64 -432 80 -448 
            LINE N 80 -448 64 -464 
            LINE N 64 -496 80 -512 
            LINE N 80 -512 64 -528 
            RECTANGLE N 64 -576 320 -64 
        END BLOCKDEF
        BEGIN BLOCKDEF ibufg
            TIMESTAMP 2001 2 2 12 53 1
            LINE N 64 0 64 -64 
            LINE N 128 -32 64 0 
            LINE N 64 -64 128 -32 
            LINE N 224 -32 128 -32 
            LINE N 0 -32 64 -32 
        END BLOCKDEF
        BEGIN BLOCKDEF bufg
            TIMESTAMP 2001 2 2 12 51 12
            LINE N 64 -64 64 0 
            LINE N 128 -32 64 -64 
            LINE N 64 0 128 -32 
            LINE N 224 -32 128 -32 
            LINE N 0 -32 64 -32 
        END BLOCKDEF
        BEGIN BLOCKDEF gnd
            TIMESTAMP 2001 2 2 12 52 44
            LINE N 64 -64 64 -96 
            LINE N 76 -48 52 -48 
            LINE N 68 -32 60 -32 
            LINE N 88 -64 40 -64 
            LINE N 64 -64 64 -80 
            LINE N 64 -128 64 -96 
        END BLOCKDEF
        BEGIN BLOCK XLXI_1 clkdll
            PIN CLKFB fosc60m
            PIN CLKIN XLXN_2
            PIN RST XLXN_4
            PIN CLK0 XLXN_1
            PIN CLK180
            PIN CLK270
            PIN CLK2X
            PIN CLK90
            PIN CLKDV
            PIN LOCKED
        END BLOCK
        BEGIN BLOCK XLXI_2 ibufg
            PIN I fosc
            PIN O XLXN_2
        END BLOCK
        BEGIN BLOCK XLXI_3 bufg
            PIN I XLXN_1
            PIN O fosc60m
        END BLOCK
        BEGIN BLOCK XLXI_4 gnd
            PIN G XLXN_4
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        INSTANCE XLXI_1 1680 1248 R0
        INSTANCE XLXI_2 1216 752 R0
        INSTANCE XLXI_3 2208 768 R0
        BEGIN BRANCH XLXN_1
            WIRE 2064 736 2208 736
        END BRANCH
        BEGIN BRANCH XLXN_2
            WIRE 1440 720 1552 720
            WIRE 1552 720 1552 736
            WIRE 1552 736 1680 736
        END BRANCH
        BEGIN BRANCH fosc60m
            WIRE 1616 800 1680 800
            WIRE 1616 800 1616 1248
            WIRE 1616 1248 2512 1248
            WIRE 2432 736 2512 736
            WIRE 2512 736 2512 1248
            WIRE 2512 736 2544 736
        END BRANCH
        INSTANCE XLXI_4 1584 1264 R0
        BEGIN BRANCH XLXN_4
            WIRE 1648 1120 1680 1120
            WIRE 1648 1120 1648 1136
        END BRANCH
        IOMARKER 2544 736 fosc60m R0 28
        BEGIN BRANCH fosc
            WIRE 1184 720 1216 720
        END BRANCH
        IOMARKER 1184 720 fosc R180 28
    END SHEET
END SCHEMATIC