rece18.vhd

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

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-- Company: 
-- Engineer:
--
-- Create Date:    10:55:12 09/29/08
-- Design Name:    
-- Module Name:    rece18 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rece18 is
port(
	--	grst 					: in std_logic;
		fosc60m  			: in std_logic;
		rclk 					: in std_logic;
		lock 					: in std_logic;
		rout 					: in std_logic_vector(17 downto 0); 
		ren 					: out std_logic;
		den 					: out std_logic;
		rpwdn 				: out std_logic;
		tpwdn 				: out std_logic; 
--	   refclk            : out std_logic;
		line_le 				: out std_logic;
		led1				   : out std_logic;
		dout 					: out std_logic_vector(17 downto 0); 
		local_le 			: out std_logic

		);
end rece18;

architecture Behavioral of rece18 is
--  	signal rclk 				: std_logic;
--	   signal f_rout 				: std_logic_vector(7 downto 0);
--		signal lock_count 		: std_logic_vector(1 downto 0);
--		signal f_lock 				: std_logic;
--  	signal rclk_count 		: std_logic_vector(1 downto 0);
		signal f_datain :std_logic_vector(17 downto 0); 
		signal a: std_logic_vector(7 downto 0);
		signal b: std_logic_vector(7 downto 0);


begin
		ren <= '1';
		den <= '1';
		tpwdn <= '1';
		rpwdn <= '1';
		line_le <= '0';																				                                                                                                                                                                      
		local_le <= '0';
		--refclk<=fosc60m;
 --   f_rclk<=rclk;
 main:process(rclk,lock,f_datain,a,b) 
-- variable	count: std_logic_vector(7 downto 0);
--	variable	 f_rout: std_logic_vector(7 downto 0);
-- variable	 b: std_logic_vector(7 downto 0);
 begin 
		
		 if lock='1' then
		    	f_datain<="000000000000000000"; 
 		     else if	rclk'event and rclk ='0' then 
                  f_datain(17 downto 16)<=rout(17 downto 16);
						f_datain(15 downto 8) <=rout(15 downto 8);
						f_datain(7 downto 0)<=rout(7 downto 0);
                  a<=f_datain(7 downto 0)+1;
                  b<=rout(7 downto 0);
						dout<=rout;
						
					 if f_datain(17 downto 16)="11" and f_datain(15 downto 8)="00000000"	then 
			      	if b=a then
			    	    led1 <= '0' ;
                else  led1 <= '1' ;
			    end if;
					 end if;
					 	 end if;

		end if;
   
end process main;


 end Behavioral;