global.h

来自「一个MIPS虚拟机的源码」· C头文件 代码 · 共 270 行

#ifndef GLOBAL_H
#define GLOBAL_H
#include  <stdio.h>
#include  <string.h>
#include  <time.h>
#include  <stdlib.h>
  #include<unistd.h>
#include<sys/types.h>
#include<sys/stat.h>
#include<fcntl.h>


#include "type.h"
#include "regdef.h"
#include "cpu.h"
#include "cp0.h"
#include "interrcontrol.h"
#include "console.h"
#include "dongfeng.h"
#include "debug.h"




/*some constant */
#define true 1
#define false 0
#define BIGEND 1
#define LITTLEEND 0

/*some mask*/
/*
#define index 0
#define raddom 1
#define entrylo0 2
#define context 4
#define badvaddr 8
#define entryhi 10
#define sr 12
#define cause 13
#define epc 14
#define prid 15*/

/* 0 INDEX*/
#define CP0_INDEX_P_MASK  0x80000000   //bit 31
#define CP0_INDEX_INDEX_MASK 0x00003f00  //bit 13-8
#define CP0_INDEX_MASK  CP0_INDEX_P_MASK | CP0_INDEX_INDEX_MASK


/* 1 random*/
#define CP0_RANDOM_RANDOM_MASK 0x00003f00  //bit 13-8
#define CP0_RANDOM_UPPER_BOUND 63
#define CP0_RANDOM_LOWER_BOUND 8
#define CP0_RANDOM_MASK CP0_RANDOM_RANDOM_MASK

/*2 entrylo*/
#define CP0_ENTRYLO_PFN_MASK 0xfffff000  //bit 31-12
#define CP0_ENTRYLO_N_MASK     0x00000800  //bit 11
#define CP0_ENTRYLO_D_MASK     0x00000400  //bit 10
#define CP0_ENTRYLO_V_MASK     0x00000200  //bit 9
#define CP0_ENTRYLO_G_MASK     0x00000100  //bit 8
#define CP0_ENTRYLO_MASK CP0_ENTRYLO_PFN_MASK| \
			CP0_ENTRYLO_N_MASK|CP0_ENTRYLO_D_MASK| \
			CP0_ENTRYLO_V_MASK|CP0_ENTRYLO_G_MASK


/*4  context*/
#define CP0_CONTEXT_PTEBASE_MASK  0xffe00000  //bit 31-21
#define CP0_CONTEXT_BADVPN_MASK  0x001ffffc   //bit 20-2
#define CP0_CONTEXT_MASK CP0_CONTEXT_PTEBASE_MASK|CP0_CONTEXT_BADVPN_MASK

/* 8 bad vaddr*/
#define CP0_BADVADDR_MASK 0xffffffff  


/* 10 entryhi*/
#define CP0_ENTRYHI_VPN_MASK 0xfffff000   //bit 31-12
#define CP0_ENTRYHI_ASID_MASK 0x00000fc0  //bit 11-6
#define CP0_ENTRYHI_MASK CP0_ENTRYHI_VPN_MASK|CP0_ENTRYHI_ASID_MASK

/*12  SR */
#define CP0_SR_CU1_MASK 	0x20000000   //bit 29
#define CP0_SR_CU0_MASK 	0x10000000   //bit 28
#define CP0_SR_RE_MASK		0x02000000    //bit 25
#define CP0_SR_BEV_MASK 	0x00400000   //bit 22
#define CP0_SR_TS_MASK 		0x00200000    //bit 21    shut down TLB
#define CP0_SR_PE_MASK 		0x00100000   //bit 20
#define CP0_SR_CM_MASK		0x00080000  //bit 19  
#define CP0_SR_PZ_MASK  	0x00040000  //bit 18
#define CP0_SR_SWC_MASK 	0x00020000  //bit 17
#define CP0_SR_ISC_MASK 	0x00010000   //bit 16
#define CP0_SR_IM_MASK 		0x0000ff00    //bit 15-8
#define CP0_SR_KUO_MASK 	0x00000020  //bit 5
#define CP0_SR_IEO_MASK 	0x00000010  //bit4
#define CP0_SR_KUP_MASK 	0x00000008  //bit 3
#define CP0_SR_IEP_MASK 	0x00000004  //bit2
#define CP0_SR_KUC_MASK 	0x00000002  //bit1
#define CP0_SR_IEC_MASK 	0x00000001  //bit 0
#define CP0_SR_MASK CP0_SR_CU1_MASK|CP0_SR_CU0_MASK| \
					CP0_SR_RE_MASK|CP0_SR_BEV_MASK|\
					CP0_SR_TS_MASK|CP0_SR_PE_MASK|\
					CP0_SR_CM_MASK|CP0_SR_PZ_MASK|\
					CP0_SR_SWC_MASK|CP0_SR_ISC_MASK|\
					CP0_SR_IM_MASK| \
					CP0_SR_KUO_MASK | CP0_SR_IEO_MASK |\
					CP0_SR_KUP_MASK | CP0_SR_IEP_MASK |\
					CP0_SR_KUC_MASK | CP0_SR_IEC_MASK
					



/* 13 CAUSE*/
#define CP0_CAUSE_BD_MASK 0x80000000  //bit 31
#define CP0_CAUSE_CE_MASK 0x30000000  //bit 29-28
#define CP0_CAUSE_IP_MASK 	0x0000ff00   //bit 15-8
#define CP0_CAUSE_EXCCODE_MASK 0x0000007c  //6-2
#define CP0_CAUSE_MASK CP0_CAUSE_BD_MASK|CP0_CAUSE_CE_MASK|\
						CP0_CAUSE_IP_MASK |CP0_CAUSE_EXCCODE_MASK 

/* 14 EPC*/
#define CP0_EPC_MASK 0xffffffff 


/* 15 PRID */
#define CP0_PRID_IMP_MASK 0x0000ff00
#define CP0_PRID_REV_MASK 0x000000ff
#define CP0_PRID_MASK CP0_PRID_IMP_MASK|CP0_PRID_REV_MASK




/*Some target machine parameters*/
#define ROM_SIZE 4096	
#define ROM_RESET_BASE_ADDR 0xbfc00000
#define ROM_LOWER_BOUND 0x1fc00000
#define ROM_UPPER_BOUND 0x1fc00fff
#define RAM_SIZE 4194304  
#define RAM_UPPER_BOUND 0x003fffff
#define RAM_LOWER_BOUND 0x00000000
#define DCACHE_SIZE 32768
#define ICACHE_SIZE 32768
#define TLBENTRY_NO 64
#define CPU_REGISTER_NUMBER 32
#define CP0_REGISTER_NUMBER 32    // in fact in mips r3k, we only use 16 cp0 resgisters




/*used in vaddr -> phyaddr*/
#define KUSEG 1          
#define KSEG0 2
#define KSEG1 3
#define KSEG2 4
#define KSEG0_V2P_CONST 0x80000000
#define KSEG1_V2P_CONST 0xa0000000 
#define DATA_LOAD 1
#define DATA_STORE 2
#define INSTRUCTION_LOAD 3
#define INSTRUCTION_STORE 4  //for swc mode

/*used in exception handler*/
#define INT 0
#define MOD 1
#define TLBL 2
#define TLBS 3
#define ADEL 4
#define ADES 5
#define IBE 6
#define DBE 7
#define SYSCAL 8
#define BP 9
#define RI 10
#define CPU 11
#define OV 12
#define TRAP 13
#define VCEI 14
#define FPE 15
#define C2E 16
#define WATCH 23

/*some global variable*/
EXTERN int host_end;
EXTERN int target_end;

EXTERN UINT32 PC;

EXTERN UINT32 cpu_register[CPU_REGISTER_NUMBER];
EXTERN UINT32 cp0_register[CP0_REGISTER_NUMBER];
EXTERN UINT32 hi;
EXTERN UINT32 lo;

EXTERN UINT8 rom[ROM_SIZE];
EXTERN UINT8 ram[RAM_SIZE];

EXTERN CACHE icache[ICACHE_SIZE/4];
EXTERN CACHE dcache[DCACHE_SIZE/4];
#define DCACHE_MASK 0x00007ffc    //32K DCACHE
#define ICACHE_MASK 0x00007ffc    //32K ICACHE
#define CACHE_VALID_MASK 0x00000001

EXTERN TLB_ENTRY tlb[TLBENTRY_NO];
EXTERN TLB_MISS tlb_miss_type; 

EXTERN OPTIONS options;

EXTERN DELAY_STATE delay_state;
EXTERN UINT32 delay_pc;

/*for console*/
EXTERN console_type console;
#define CONSOLE_KEYBORD_UNREADY 0x00000000
#define CONSOLE_KEYBORD_READY 0x00000001
#define CONSOLE_DISPLAY_UNREADY 0x00000000
#define CONSOLE_DISPLAY_READY 0x00000001
#define CONSOLE_DISPLAY_DATA_MASK 0x000000ff
#define CONSOLE_KEYBORD_DATA_MASK 0x000000ff
#define CONSOLE_LOWER_ADDR 0x02000000
#define CONSOLE_UPPER_ADDR 0x0200000f
#define KEYBORD_READY_TIME 40000000   //40ms=40000000ns
#define DISPLAY_READY_TIME 40000000    //40ms=40000000ns
#define TIME_PER_INSTRUCTION  10000 // //time used perinstruction. we assume in one second, dongfeng 
									      //execute 1M instructions. That is 1MIPS. so this value is 10^3ns
#define KEYBOARD_CONTROL  	0x00000000
#define KEYBOARD_DATA     	0x00000004
#define DISPLAY_CONTROL   	0x00000008
#define DISPLAY_DATA      	0x0000000C
#define INTERRUPT_ENABLE 0x00000002





/*for pending pask*/
#define MAX_PENDING_TASK 10
EXTERN task_type  pending_task[MAX_PENDING_TASK];
EXTERN int pending_task_number;

/*for interrupt control*/
EXTERN interrupt_controller_type interrupt_controller;

/*for exception*/
EXTERN boolean exception_padding;
EXTERN UINT32 exception_pc;

/*for interrupt controller */
#define IRQ7 0x00008000
#define IRQ6 0x00004000
#define IRQ5 0x00002000
#define IRQ4 0x00001000   //to display
#define IRQ3 0x00000800  //to keybord
#define IRQ2 0x00000400
#define IRQ1 0x00000200
#define IRQ0 0x00000100

EXTERN boolean halt_machine;

/*for  debug*/
EXTERN debug_type debug;


/*some function*/
UINT32 bytes2word(UINT8   baseaddr[]);
void word2bytes(UINT32 data, UINT8  baseaddr[]);
int random_value(int lowbound,int uppbound);
void mult_unsigned(UINT32 * high,UINT32 * low,UINT32 rs, UINT32 rd);
void mult_signed(UINT32 * high,UINT32 * low, INT32 rs, INT32 rd);
UINT8 get_byte_from_word(UINT32 word,UINT8 offset);

#endif