📄 cpu.c
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boolean cache_able;
UINT32 reg_data,mem_data;
UINT8 word_offset;
offset = get_offset(instruction);
base_addr = cpu_register[get_rb(instruction)];
vaddr = base_addr + offset;
reg_data = cpu_register[get_rt(instruction)];
if ((options.debug_mode==true) && (debug.current_mode==STEP))
printf("%s %s,0x%x(%s)","swl",reg_table[get_rt(instruction)],offset, reg_table[get_rb(instruction)]);
if ((vaddr % 4)!=0)
{
//fprintf(stderr,"vaddr % 4- !=0---------------------------------!\n");
//bad address exctiption
//if ((operation_mode==DATA_LOAD)||(operation_mode==INSTRUCTION_LOAD))
// exception(ADEL,-1);
//else
exception(ADES,-1);
return ;
}
phyaddr = vaddr2phyaddr(vaddr,DATA_STORE,&cache_able);
if ((vaddr % 4)!=0)
{
//fprintf(stderr,"vaddr % 4- !=0---------------------------------!\n");
//bad address exctiption
//if ((operation_mode==DATA_LOAD)||(operation_mode==INSTRUCTION_LOAD))
// exception(ADEL,-1);
//else
exception(ADES,-1);
return ;
}
if (0xffffffff== phyaddr ){
//an exception has occured
}
else {
if (load_word(vaddr,phyaddr,cache_able,DATA_STORE,&mem_data))
{
word_offset = vaddr & 0x00000003;
store_word(vaddr,phyaddr, cache_able, DATA_STORE,swl(reg_data, mem_data, word_offset));
}
}
}
/*opcode = 43 sw t,0(b)*/
static void sw_simulate(const UINT32 instruction)
{
UINT32 base_addr,vaddr,phyaddr;
INT32 offset;
boolean cache_able;
UINT32 reg_data;
offset = get_offset(instruction);
base_addr = cpu_register[get_rb(instruction)];
vaddr = base_addr + offset;
reg_data = cpu_register[get_rt(instruction)];
if ((options.debug_mode==true) && (debug.current_mode==STEP))
printf("%s %s,0x%x(%s)","sw",reg_table[get_rt(instruction)],offset, reg_table[get_rb(instruction)]);
if ((vaddr % 4)!=0)
{
//fprintf(stderr,"vaddr % 4- !=0---------------------------------!\n");
//bad address exctiption
//if ((operation_mode==DATA_LOAD)||(operation_mode==INSTRUCTION_LOAD))
// exception(ADEL,-1);
//else
exception(ADES,-1);
return ;
}
//
//
//printf("vaddr %x\n",vaddr);
phyaddr = vaddr2phyaddr(vaddr,DATA_STORE,&cache_able);
//printf("phyaddr %x\n",phyaddr);
if ((vaddr % 4)!=0)
{
//fprintf(stderr,"vaddr % 4- !=0---------------------------------!\n");
//bad address exctiption
//if ((operation_mode==DATA_LOAD)||(operation_mode==INSTRUCTION_LOAD))
// exception(ADEL,-1);
//else
exception(ADES,-1);
return ;
}
//printf("phyaddr %x",phyaddr);
if (0xffffffff== phyaddr ){
//an exception has occured
}
else {
store_word(vaddr,phyaddr, cache_able, DATA_STORE,reg_data);
}
}
/*opcode = 44 sdl t,0(b) MIPSIII*/
/*opcode = 45 sdr t,0(b) MIPSIII*/
/*opcode = 46 swr t,0(b)*/
static void swr_simulate(const UINT32 instruction)
{
UINT32 base_addr,vaddr,phyaddr;
INT32 offset;
boolean cache_able;
UINT32 reg_data,mem_data;
UINT8 word_offset;
offset = get_offset(instruction);
base_addr = cpu_register[get_rb(instruction)];
vaddr = base_addr + offset;
reg_data = cpu_register[get_rt(instruction)];
if ((options.debug_mode==true) && (debug.current_mode==STEP))
printf("%s %s,0x%x(%s)","swr",reg_table[get_rt(instruction)],offset, reg_table[get_rb(instruction)]);
if ((vaddr % 4)!=0)
{
//fprintf(stderr,"vaddr % 4- !=0---------------------------------!\n");
//bad address exctiption
//if ((operation_mode==DATA_LOAD)||(operation_mode==INSTRUCTION_LOAD))
// exception(ADEL,-1);
//else
exception(ADES,-1);
return ;
}
phyaddr = vaddr2phyaddr(vaddr,DATA_STORE,&cache_able);
if ((phyaddr % 4)!=0)
{
//fprintf(stderr,"vaddr % 4- !=0---------------------------------!\n");
//bad address exctiption
//if ((operation_mode==DATA_LOAD)||(operation_mode==INSTRUCTION_LOAD))
// exception(ADEL,-1);
//else
exception(ADES,-1);
return ;
}
if (0xffffffff== phyaddr ){
//an exception has occured
}
else {
if (load_word(vaddr,phyaddr,cache_able,DATA_STORE,&mem_data)){
word_offset = vaddr & 0x00000003;
store_word(vaddr,phyaddr, cache_able, DATA_STORE,swr(reg_data, mem_data, word_offset));
}
}
}
static void fp_instruction()
{
// CU1 CpU instruction .
exception(CPU,1);
}
static void cu2_instruction()
{
// CU2 CpU instruction .
exception(CPU,2);
}
static void ri_instruction()
{
exception(RI,-1);
}
/*all instructions' simualtion--------------------------------- end */
static void opcode0_instruction(const UINT32 instruction)
{
UINT16 sub_opcode;
sub_opcode = get_sub_opcode(instruction);
//printf("sub_opcode %x\n",sub_opcode);
//printf("sub_opcode %d\n",sub_opcode);
switch (sub_opcode)
{
case 0:
sll_simulate(instruction);
break;
/*1 mips iv*/
case 2:
srl_simulate(instruction);
break;
case 3:
sra_simulate(instruction);
break;
case 4:
sllv_simulate(instruction);
break;
/*5 mini risc-4010*/
case 6:
srlv_simulate(instruction);
break;
case 7:
srav_simulate(instruction);
break;
case 8:
jr_simulate(instruction);
break;
case 9:
jalr_simulate(instruction);
break;
/*10 11 MIPS IV*/
case 12:
syscall_simulate(instruction);
break;
case 13:
break_simulate(instruction);
break;
/*14 MIPS II*/
/*15 sync */
case 16:
mfhi_simulate(instruction);
break;
case 17:
mthi_simulate(instruction);
break;
case 18:
mflo_simulate(instruction);
break;
case 19:
mtlo_simulate(instruction);
break;
/* 20 21 22 23 MIPS III*/
case 24:
mult_simulate(instruction);
break;
case 25:
multu_simulate(instruction);
break;
case 26:
div_simulate(instruction);
break;
case 27:
divu_simulate(instruction);
break;
/*28 29 30 31 MIPS III*/
case 32:
add_simulate(instruction);
break;
case 33:
addu_simulate(instruction);
//printf("return from addu_simulate");
break;
case 34:
sub_simulate(instruction);
break;
case 35:
subu_simulate(instruction);
break;
case 36:
and_simulate(instruction);
break;
case 37:
or_simulate(instruction);
break;
case 38:
xor_simulate(instruction);
break;
case 39:
nor_simulate(instruction);
break;
/*40 41 VR4100*/
case 42:
slt_simulate(instruction);
break;
case 43:
sltu_simulate(instruction);
break;
/*44-63 MIPS III*/
default:
ri_instruction();
break;
}
//printf("return from 0\n");
}
static void opcode1_instruction(const UINT32 instruction)
{
UINT16 rt_code;
rt_code = get_rt(instruction);
//printf("rt_code %d",rt_code);
switch(rt_code)
{
case 0:
bltz_simulate(instruction);
break;
case 1:
bgez_simulate(instruction);
break;
/*2-15 MIPS II*/
case 16:
bltzal_simulate(instruction);
break;
case 17:
bgezal_simulate(instruction);
break;
/*18 19 MIPS II*/
default:
ri_instruction();
break;
}
}
static void opcode16_rscode16_instruction(const UINT32 instruction)
{
UINT16 sub_opcode;
sub_opcode = get_sub_opcode(instruction);
switch (sub_opcode)
{
case 1:
tlbr_simulate(instruction);
break;
case 2:
tlbwi_simulate(instruction);
break;
case 6:
tlbwr_simulate(instruction);
break;
case 8:
tlbp_simulate(instruction);
break;
case 16:
rfe_simulate(instruction);
break;
default:
ri_instruction();
break;
}
}
static void opcode16_instruction(const UINT32 instruction)
{
UINT16 rs_code;
rs_code = get_rs(instruction);
switch (rs_code)
{
case 0:
mfc0_simulate( instruction);
break;
/*1 MIPS III*/
/* 2 cfc0 not implemented*/
/*3 not defined*/
case 4:
mtc0_simulate(instruction);
break;
/*5 MIPSIII*/
/*6 ctc0 not implemented*/
case 16:
opcode16_rscode16_instruction(instruction);
break;
default:
ri_instruction();
break;
}
}
static void opcode17_instruction(const UINT32 instruction)
{
fp_instruction();
}
static void opcode18_instruction(const UINT32 instruction)
{
cu2_instruction();
}
static void opcode19_instruction(const UINT32 instruction)
{
fp_instruction();
}
static boolean cpu_step(UINT32 phyaddr,boolean cache_able)
{
UINT32 instruction;
UINT16 op_code;
int adsf;
exception_padding==false;
if (!cpu_fetch_instruction(&instruction,phyaddr,cache_able))
{
//an exception occured.
fprintf(stderr,"Error cpu_fetch_instruction(),aborting\n ");
}
//printf("instruction %x\n",instruction);
op_code = get_op_code(instruction);
//printf("op_code %x\n",op_code);
if ((options.debug_mode==true) && (debug.current_mode==STEP))
printf("PC = 0x%x [",PC);
switch (op_code)
{
case 0:
opcode0_instruction(instruction);
break;
case 1:
opcode1_instruction( instruction);
break;
case 2:
j_simulate(instruction);
break;
case 3:
jal_simulate(instruction);
break;
case 4:
beq_simulate(instruction);
break;
case 5:
bne_simulate(instruction);
break;
case 6:
blez_simulate(instruction);
break;
case 7:
bgtz_simulate(instruction);
break;
case 8:
addi_simulate(instruction);
break;
case 9:
addiu_simulate(instruction);
break;
case 10:
slti_simulate(instruction);
break;
case 11:
sltiu_simulate(instruction);
break;
case 12:
andi_simulate(instruction);
break;
case 13:
ori_simulate(instruction);
break;
case 14:
xori_simulate( instruction);
break;
case 15:
lui_simulate(instruction);
break;
case 16:
opcode16_instruction(instruction);
break;
case 17:
opcode17_instruction(instruction);
break;
case 18:
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