timer.c

Bacnet protocol stack for linux

    /*          11 (each edge of TIOA) */
    /* */
    /*  RB LOADING SELECTION */
    /*  LDRB  = 00 (none)                  <===== take default */
    /*          01 (rising edge of TIOA) */
    /*          10 (falling edge of TIOA) */
    /*          11 (each edge of TIOA) */
    /* */
    /* TCCLKS = 1 (TIMER_CLOCK5) */
    /* CPCTRG = 1 (RC Compare resets the counter and restarts the clock) */
    /* WAVE   = 0 (Capture mode enabled) */
    pTC->TC_CMR = 0x4004;

    /*        TC Register C     TC_RC   (read/write)   Compare Register 16-bits */
    /* */
    /*    |----------------------------------|----------------------------------------| */
    /*    |           not used                               RC                       | */
    /*    |----------------------------------|----------------------------------------| */
    /*   31                              16 15                                    0 */
    /* */
    /*    Timer Calculation:   What count gives 1 msec time-out? */
    /* */
    /*    TIMER_CLOCK5 = MCK / 1024  = 48054841 / 1024  =  46928 hz */
    /* */
    /*    TIMER_CLOCK5 Period = 1 / 46928  =  21.309239686 microseconds */
    /* */
    /*    A little algebra:  .001 sec = count * 21.3092396896*10**-6 */
    /*                        count =  .001 / 21.3092396896*10**-6 */
    /*                        count =  46.928 */
    /* */
    /*    STK: Even Simpler, let the compiler do the work: */
    /* */
    /*    TIMER_CLOCK5 = (MCK / 1024) / 1000 */
    /*                 = 48054841 / 1024 / 1000 =  46.928 */
    pTC->TC_RC = ((MCK / 1024 / 1000) + 1) * milliseconds;

    /*        TC Interrupt Enable Register  TC_IER    (write-only) */
    /* */
    /* */
    /*    |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
    /*    |              ETRGS   LDRBS   LDRAS   CPCS    CPBS      CPAS     LOVRS    COVFS | */
    /*    |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
    /*   31         8    7       6       5       4        3        2        1        0 */
    /* */
    /*  COVFS    = 0  no effect    <===== take  default */
    /*             1  enable counter overflow interrupt */
    /* */
    /*  LOVRS    = 0  no effect    <===== take  default */
    /*             1  enable load overrun interrupt */
    /* */
    /*  CPAS     = 0  no effect    <===== take  default */
    /*             1  enable RA compare interrupt */
    /* */
    /*  CPBS     = 0  no effect    <===== take  default */
    /*             1  enable RB compare interrupt */
    /* */
    /*  CPCS     = 0  no effect */
    /*             1  enable RC compare interrupt    <===== we select this one */
    /* */
    /*  LDRAS    = 0  no effect    <===== take  default */
    /*             1  enable RA load interrupt */
    /* */
    /*  LDRBS    = 0  no effect    <===== take  default */
    /*             1  enable RB load interrupt */
    /* */
    /*  ETRGS    = 0  no effect    <===== take  default */
    /*             1  enable External Trigger interrupt */
    /* */
    /* enable RC compare interrupt */
    pTC->TC_IER = 0x10;

    /*        TC Interrupt Disable Register  TC_IDR    (write-only) */
    /* */
    /* */
    /*    |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
    /*    |              ETRGS   LDRBS   LDRAS   CPCS    CPBS      CPAS     LOVRS    COVFS | */
    /*    |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
    /*   31         8    7       6       5       4        3        2        1        0 */
    /* */
    /*  COVFS    = 0  no effect */
    /*             1  disable counter overflow interrupt    <===== we select this one */
    /* */
    /*  LOVRS    = 0  no effect */
    /*             1  disable load overrun interrupt    <===== we select this one */
    /* */
    /*  CPAS     = 0  no effect */
    /*             1  disable RA compare interrupt    <===== we select this one */
    /* */
    /*  CPBS     = 0  no effect */
    /*             1  disable RB compare interrupt    <===== we select this one */
    /* */
    /*  CPCS     = 0  no effect    <===== take  default */
    /*             1  disable RC compare interrupt */
    /* */
    /*  LDRAS    = 0  no effect */
    /*             1  disable RA load interrupt    <===== we select this one */
    /* */
    /*  LDRBS    = 0  no effect */
    /*             1  disable RB load interrupt    <===== we select this one */
    /* */
    /*  ETRGS    = 0  no effect */
    /*             1  disable External Trigger interrupt    <===== we select this one */
    /* */
    /* disable all except RC compare interrupt */
    pTC->TC_IDR = 0xEF;
}

/*  ***************************************************************************** */
/* */
/*     Timer 0 Interrupt Service Routine */
/* */
/*     Entered when Timer0 RC compare interrupt asserts */
/* */
/*  Author:  James P Lynch  May 12, 2007 */
/*  Modified by Steve Karg */
/*    simplified and changed to a millisecond count-up timer */
/*  ***************************************************************************** */
static void Timer0IrqHandler(
    void)
{

    volatile AT91PS_TC pTC = AT91C_BASE_TC0;    /* pointer to timer channel 0 register structure */
    unsigned int dummy; /* temporary */

    /* read TC0 Status Register to clear interrupt */
    dummy = pTC->TC_SR;
    /* increment the tick count */
    Timer_Milliseconds++;
    if (SilenceTime < 60000)
        SilenceTime++;
}

int Timer_Silence(
    void)
{
    return SilenceTime;
}

void Timer_Silence_Reset(
    void)
{
    SilenceTime = 0;
}

/*  ***************************************************************************** */
/* */
/*     Timer 0 Initialization */
/* */
/*  From James P Lynch main.c example code */
/*  Modified by Steve Karg */
/*    Moved timer startup code from main */
/*    modified the peripheral clock init */
/*  ***************************************************************************** */
void TimerInit(
    void)
{
    /* enable the Timer0 peripheral clock */
    volatile AT91PS_PMC pPMC = AT91C_BASE_PMC;
    pPMC->PMC_PCER = pPMC->PMC_PCSR | (1 << AT91C_ID_TC0);
    /* Set up the AIC  registers for Timer 0 */
    volatile AT91PS_AIC pAIC = AT91C_BASE_AIC;
    /* Disable timer 0 interrupt */
    /* in AIC Interrupt Disable Command Register */
    pAIC->AIC_IDCR = (1 << AT91C_ID_TC0);
    /* Set the TC0 IRQ handler address in */
    /* AIC Source Vector Register[12] */
    pAIC->AIC_SVR[AT91C_ID_TC0] = (unsigned int) Timer0IrqHandler;
    /* Set the interrupt source type and priority */
    /* in AIC Source Mode Register[12] */
    pAIC->AIC_SMR[AT91C_ID_TC0] =
        (AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 0x4);
    /* Clear the TC0 interrupt */
    /* in AIC Interrupt Clear Command Register */
    pAIC->AIC_ICCR = (1 << AT91C_ID_TC0);
    /* Remove disable timer 0 interrupt */
    /* in AIC Interrupt Disable Command Reg */
    pAIC->AIC_IDCR = (0 << AT91C_ID_TC0);
    /* Enable the TC0 interrupt */
    /* in AIC Interrupt Enable Command Register */
    pAIC->AIC_IECR = (1 << AT91C_ID_TC0);
    /* Setup timer0 to generate a 1 msec periodic interrupt */
    Timer0_Setup(1);
}