📄 at91sam7s256.h
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#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */
#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) /* (SPI) Chip Select Active After Transfer */
#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */
#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */
#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */
#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */
#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */
#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */
#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */
#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */
#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */
#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */
#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
/* ***************************************************************************** */
typedef struct _AT91S_ADC {
AT91_REG ADC_CR; /* ADC Control Register */
AT91_REG ADC_MR; /* ADC Mode Register */
AT91_REG Reserved0[2]; /* */
AT91_REG ADC_CHER; /* ADC Channel Enable Register */
AT91_REG ADC_CHDR; /* ADC Channel Disable Register */
AT91_REG ADC_CHSR; /* ADC Channel Status Register */
AT91_REG ADC_SR; /* ADC Status Register */
AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */
AT91_REG ADC_IER; /* ADC Interrupt Enable Register */
AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */
AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */
AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */
AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */
AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */
AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */
AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */
AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */
AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */
AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */
AT91_REG Reserved1[44]; /* */
AT91_REG ADC_RPR; /* Receive Pointer Register */
AT91_REG ADC_RCR; /* Receive Counter Register */
AT91_REG ADC_TPR; /* Transmit Pointer Register */
AT91_REG ADC_TCR; /* Transmit Counter Register */
AT91_REG ADC_RNPR; /* Receive Next Pointer Register */
AT91_REG ADC_RNCR; /* Receive Next Counter Register */
AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */
AT91_REG ADC_TNCR; /* Transmit Next Counter Register */
AT91_REG ADC_PTCR; /* PDC Transfer Control Register */
AT91_REG ADC_PTSR; /* PDC Transfer Status Register */
} AT91S_ADC,
*AT91PS_ADC;
/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) /* (ADC) Software Reset */
#define AT91C_ADC_START ((unsigned int) 0x1 << 1) /* (ADC) Start Conversion */
/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) /* (ADC) Trigger Enable */
#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) /* (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software */
#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) /* (ADC) Trigger Selection */
#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) /* (ADC) Selected TRGSEL = TIAO0 */
#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) /* (ADC) Selected TRGSEL = TIAO1 */
#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) /* (ADC) Selected TRGSEL = TIAO2 */
#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) /* (ADC) Selected TRGSEL = TIAO3 */
#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) /* (ADC) Selected TRGSEL = TIAO4 */
#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) /* (ADC) Selected TRGSEL = TIAO5 */
#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) /* (ADC) Selected TRGSEL = External Trigger */
#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) /* (ADC) Resolution. */
#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) /* (ADC) 10-bit resolution */
#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) /* (ADC) 8-bit resolution */
#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) /* (ADC) Sleep Mode */
#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) /* (ADC) Normal Mode */
#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) /* (ADC) Sleep Mode */
#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) /* (ADC) Prescaler rate selection */
#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) /* (ADC) Startup Time */
#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) /* (ADC) Sample & Hold Time */
/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) /* (ADC) Channel 0 */
#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) /* (ADC) Channel 1 */
#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) /* (ADC) Channel 2 */
#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) /* (ADC) Channel 3 */
#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) /* (ADC) Channel 4 */
#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) /* (ADC) Channel 5 */
#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) /* (ADC) Channel 6 */
#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) /* (ADC) Channel 7 */
/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) /* (ADC) End of Conversion */
#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) /* (ADC) End of Conversion */
#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) /* (ADC) End of Conversion */
#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) /* (ADC) End of Conversion */
#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) /* (ADC) End of Conversion */
#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) /* (ADC) End of Conversion */
#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) /* (ADC) End of Conversion */
#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) /* (ADC) End of Conversion */
#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) /* (ADC) Overrun Error */
#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) /* (ADC) Overrun Error */
#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) /* (ADC) Overrun Error */
#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) /* (ADC) Overrun Error */
#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) /* (ADC) Overrun Error */
#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) /* (ADC) Overrun Error */
#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) /* (ADC) Overrun Error */
#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) /* (ADC) Overrun Error */
#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) /* (ADC) Data Ready */
#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) /* (ADC) General Overrun */
#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) /* (ADC) End of Receiver Transfer */
#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) /* (ADC) RXBUFF Interrupt */
/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) /* (ADC) Last Data Converted */
/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) /* (ADC) Converted Data */
/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
/* ***************************************************************************** */
typedef struct _AT91S_SSC {
AT91_REG SSC_CR; /* Control Register */
AT91_REG SSC_CMR; /* Clock Mode Register */
AT91_REG Reserved0[2]; /* */
AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */
AT91_REG SSC_RFMR; /* Receive Frame Mode Register */
AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */
AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */
AT91_REG SSC_RHR; /* Receive Holding Register */
AT91_REG SSC_THR; /* Transmit Holding Register */
AT91_REG Reserved1[2]; /* */
AT91_REG SSC_RSHR; /* Receive Sync Holding Register */
AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */
AT91_REG Reserved2[2]; /* */
AT91_REG SSC_SR; /* Status Register */
AT91_REG SSC_IER; /* Interrupt Enable Register */
AT91_REG SSC_IDR; /* Interrupt Disable Register */
AT91_REG SSC_IMR; /* Interrupt Mask Register */
AT91_REG Reserved3[44]; /* */
AT91_REG SSC_RPR; /* Receive Pointer Register */
AT91_REG SSC_RCR; /* Receive Counter Register */
AT91_REG SSC_TPR; /* Transmit Pointer Register */
AT91_REG SSC_TCR; /* Transmit Counter Register */
AT91_REG SSC_RNPR; /* Receive Next Pointer Register */
AT91_REG SSC_RNCR; /* Receive Next Counter Register */
AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */
AT91_REG SSC_TNCR; /* Transmit Next Counter Register */
AT91_REG SSC_PTCR; /* PDC Transfer Control Register */
AT91_REG SSC_PTSR; /* PDC Transfer Status Register */
} AT91S_SSC,
*AT91PS_SSC;
/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) /* (SSC) Receive Enable */
#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) /* (SSC) Receive Disable */
#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) /* (SSC) Transmit Enable */
#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) /* (SSC) Transmit Disable */
#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) /* (SSC) Software Reset */
/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) /* (SSC) Receive/Transmit Clock Selection */
#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) /* (SSC) Divided Clock */
#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) /* (SSC) TK Clock signal */
#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) /* (SSC) RK pin */
#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) /* (SSC) Receive/Transmit Clock Output Mode Selection */
#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) /* (SSC) Receive/Transmit Clock Inversion */
#define AT91C_SSC_START ((unsigned int) 0xF << 8) /* (SSC) Receive/Transmit Start Selection */
#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) /* (SSC) Transmit/Receive start */
#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) /* (SSC) Detection of a low level on⌨️ 快捷键说明
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