📄 at91sam7s256.h
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AT91_REG WDTC_WDSR; /* Watchdog Status Register */
} AT91S_WDTC,
*AT91PS_WDTC;
/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) /* (WDTC) Watchdog Restart */
#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) /* (WDTC) Watchdog KEY Password */
/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) /* (WDTC) Watchdog Timer Restart */
#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) /* (WDTC) Watchdog Fault Interrupt Enable */
#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) /* (WDTC) Watchdog Reset Enable */
#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) /* (WDTC) Watchdog Timer Restart */
#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) /* (WDTC) Watchdog Disable */
#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) /* (WDTC) Watchdog Delta Value */
#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) /* (WDTC) Watchdog Debug Halt */
#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) /* (WDTC) Watchdog Idle Halt */
/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) /* (WDTC) Watchdog Underflow */
#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) /* (WDTC) Watchdog Error */
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
/* ***************************************************************************** */
typedef struct _AT91S_VREG {
AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
} AT91S_VREG,
*AT91PS_VREG;
/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) /* (VREG) Voltage Regulator Power Standby Mode */
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Memory Controller Interface */
/* ***************************************************************************** */
typedef struct _AT91S_MC {
AT91_REG MC_RCR; /* MC Remap Control Register */
AT91_REG MC_ASR; /* MC Abort Status Register */
AT91_REG MC_AASR; /* MC Abort Address Status Register */
AT91_REG Reserved0[21]; /* */
AT91_REG MC_FMR; /* MC Flash Mode Register */
AT91_REG MC_FCR; /* MC Flash Command Register */
AT91_REG MC_FSR; /* MC Flash Status Register */
} AT91S_MC,
*AT91PS_MC;
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) /* (MC) Half-word */
#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) /* (MC) Word */
#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) /* (MC) Abort Type Status */
#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) /* (MC) Data Read */
#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) /* (MC) Data Write */
#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) /* (MC) Code Fetch */
#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) /* (MC) Master 0 Abort Source */
#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) /* (MC) Master 1 Abort Source */
#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) /* (MC) Saved Master 0 Abort Source */
#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) /* (MC) Saved Master 1 Abort Source */
/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) /* (MC) Flash Ready */
#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) /* (MC) Lock Error */
#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) /* (MC) Programming Error */
#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) /* (MC) No Erase Before Programming */
#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) /* (MC) Flash Wait State */
#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) /* (MC) 1 cycle for Read, 2 for Write operations */
#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) /* (MC) 2 cycles for Read, 3 for Write operations */
#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) /* (MC) 3 cycles for Read, 4 for Write operations */
#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) /* (MC) 4 cycles for Read, 4 for Write operations */
#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) /* (MC) Flash Microsecond Cycle Number */
/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) /* (MC) Flash Command */
#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) /* (MC) Starts the programming of th epage specified by PAGEN. */
#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) /* (MC) Set General Purpose NVM bits. */
#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) /* (MC) Clear General Purpose NVM bits. */
#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) /* (MC) Set Security Bit. */
#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) /* (MC) Page Number */
#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) /* (MC) Writing Protect Key */
/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) /* (MC) Security Bit Status */
#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) /* (MC) Sector 0 Lock Status */
#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) /* (MC) Sector 1 Lock Status */
#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) /* (MC) Sector 2 Lock Status */
#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) /* (MC) Sector 3 Lock Status */
#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) /* (MC) Sector 4 Lock Status */
#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) /* (MC) Sector 5 Lock Status */
#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) /* (MC) Sector 6 Lock Status */
#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) /* (MC) Sector 7 Lock Status */
#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) /* (MC) Sector 0 Lock Status */
#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) /* (MC) Sector 1 Lock Status */
#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) /* (MC) Sector 2 Lock Status */
#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) /* (MC) Sector 3 Lock Status */
#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) /* (MC) Sector 4 Lock Status */
#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) /* (MC) Sector 5 Lock Status */
#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) /* (MC) Sector 6 Lock Status */
#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) /* (MC) Sector 7 Lock Status */
#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) /* (MC) Sector 8 Lock Status */
#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) /* (MC) Sector 9 Lock Status */
#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) /* (MC) Sector 10 Lock Status */
#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) /* (MC) Sector 11 Lock Status */
#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) /* (MC) Sector 12 Lock Status */
#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) /* (MC) Sector 13 Lock Status */
#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) /* (MC) Sector 14 Lock Status */
#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) /* (MC) Sector 15 Lock Status */
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
/* ***************************************************************************** */
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; /* Control Register */
AT91_REG SPI_MR; /* Mode Register */
AT91_REG SPI_RDR; /* Receive Data Register */
AT91_REG SPI_TDR; /* Transmit Data Register */
AT91_REG SPI_SR; /* Status Register */
AT91_REG SPI_IER; /* Interrupt Enable Register */
AT91_REG SPI_IDR; /* Interrupt Disable Register */
AT91_REG SPI_IMR; /* Interrupt Mask Register */
AT91_REG Reserved0[4]; /* */
AT91_REG SPI_CSR[4]; /* Chip Select Register */
AT91_REG Reserved1[48]; /* */
AT91_REG SPI_RPR; /* Receive Pointer Register */
AT91_REG SPI_RCR; /* Receive Counter Register */
AT91_REG SPI_TPR; /* Transmit Pointer Register */
AT91_REG SPI_TCR; /* Transmit Counter Register */
AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
AT91_REG SPI_RNCR; /* Receive Next Counter Register */
AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
} AT91S_SPI,
*AT91PS_SPI;
/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */
#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */
#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */
#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) /* (SPI) SPI Last Transfer */
/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */
#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */
#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */
#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */
#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */
#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */
#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */
#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */
#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */
#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */
#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */
#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */
#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */
#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */
#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */
#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */
#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */
#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */
#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) /* (SPI) NSSR Interrupt */
#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) /* (SPI) TXEMPTY Interrupt */
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
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