reginfo.h

ssd192Xv1 液晶驱动程序 驱动程序 彩屏液晶

#ifndef __REGINFO_H__
#define __REGINFO_H__
typedef struct tag_reginfo 
{
	unsigned char	name[48+1];
	unsigned long	offset;
	unsigned short	access_size;
	unsigned short	access_type;
	unsigned long	def;
	unsigned long	mask;
} reginfo_t;
#define ACCESS_RW	1
#define ACCESS_RO	0
#define ACCESS_WO	0
#ifndef __REGINFO__
extern reginfo_t reginfo[];
#else
reginfo_t	reginfo[] = {
	/* name, offset, access_size, access_type, default, mask */
		{"DMA", 0, 32, ACCESS_RW, 0, 0},
		{"BLOCK SIZE & DMA HOST BOUNDARY", 0x04, 16, ACCESS_RW, 0, 0x8000},
		{"COUNT", 0x06, 16, ACCESS_RW, 0, 0},
		{"ARG", 0x08, 32, ACCESS_RW, 0, 0},
		{"TRANSFER MODE", 0x0C, 16, ACCESS_RW, 0, (0xFFC8)},
		{"CMD", 0x0E, 16, ACCESS_RW, 0, (0xC004)},
		{"RSP[31..0]", 0x10, 32, ACCESS_RO, 0, 0},
		{"RSP[63..32]", 0x14, 32, ACCESS_RO, 0, 0},
		{"RSP[95..64]", 0x18, 32, ACCESS_RO, 0, 0},
		{"RSP[127..96]", 0x1C, 32, ACCESS_RO, 0, 0},
		{"DATAPORT", 0x20, 32, ACCESS_RW, 0, 0},	// tested via fifo read/write test
//In R2.0	{"PRESENT STATE", 0x24, 32, ACCESS_RO, (0x01F80C00), (0xFE00F0F8)},	// tested via another method
		{"PRESENT STATE", 0x24, 32, ACCESS_RO, (0x01F80000), (0xFE00F0F8)},	
		{"HOST CONTROL", 0x28, 8, ACCESS_RW, 0, 0xFC},
		{"SDBUS VOLTAGE SELECT", 0x29, 8, ACCESS_RW, 0, 0xF0},	// SD Bus Power pin is not tested
		{"BLOCK GAP CONTROL", 0x2A, 8, ACCESS_RW, 0, 0xFF},
		{"WAKEUP CONTROL", 0x2B, 8, ACCESS_RW, 0, 0xF8},
		{"CLOCK CONTROL", 0x2C, 8, ACCESS_RW, 0, 0xFA},
		{"FREQUENCY SELECT", 0x2D, 8, ACCESS_RW, 0, 0},	
		{"TIMEOUT CONTROL", 0x2E, 8, ACCESS_RW, 0, 0xF0},
		{"SOFTWARE RESET", 0x2F, 8, ACCESS_RW, 0, 0xF8},	// reset bits are not checked
		{"INTR STATUS", 0x30, 16, ACCESS_RO, 0, 0},		// tested in interrupt test, 'coz RW1C
		{"ERROR INTR STATUS", 0x32, 16, ACCESS_RO, 0, 0},	// tested in interrupt test, 'coz RWIC
		{"INTR STATUS ENABLE", 0x34, 16, ACCESS_RW, 0, (0xFE00)},
//		{"ERR INTR STATUS ENABLE", 0x36, 16, ACCESS_RW, 0, (0x8E00)},
		{"ERR INTR STATUS ENABLE", 0x36, 16, ACCESS_RW, 0, (0x0E00)},	// b15:12 are implemented
		{"INTR SIGNAL ENABLE", 0x38, 16, ACCESS_RW, 0, (0xFE00)},
//		{"ERR INTR SIGNAL ENABLE", 0x3A, 16, ACCESS_RW, 0, (0x8E00)},
		{"ERR INTR SIGNAL ENABLE", 0x3A, 16, ACCESS_RW, 0, (0x0E00)},	// b15:12 are implemented
		{"ACMD12 ERR STATUS", 0x3C, 16, ACCESS_RO, 0, (0xFFB0)},
		{"u16 RSVD(0x3E)", 0x3E, 16, ACCESS_RO, 0, (0xFFFF)},
//In R2.0	{"CAPABILITIES", 0x40, 32, ACCESS_RO, (0x03420080), (0xFC5CFF7F)},
		{"CAPABILITIES", 0x40, 32, ACCESS_RO, (0x05410080), (0xFFFFFFFF)},
		{"u32 RSVD (0x44)", 0x44, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x48)", 0x48, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x4C)", 0x4C, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x50)", 0x50, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x54)", 0x54, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x58)", 0x58, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x5C)", 0x5C, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x60)", 0x60, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x64)", 0x64, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x68)", 0x68, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x6C)", 0x6C, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x70)", 0x70, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x74)", 0x74, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x78)", 0x78, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x7C)", 0x7C, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x80)", 0x80, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x84)", 0x84, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x88)", 0x88, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x8C)", 0x8C, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x90)", 0x90, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x94)", 0x94, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x98)", 0x98, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0x9C)", 0x9C, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xA0)", 0xA0, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xA4)", 0xA4, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xA8)", 0xA8, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xAC)", 0xAC, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xB0)", 0xB0, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xB4)", 0xB4, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xB8)", 0xB8, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xBC)", 0xBC, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xC0)", 0xC0, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xC4)", 0xC4, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xC8)", 0xC8, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xCC)", 0xCC, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xD0)", 0xD0, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xD4)", 0xD4, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xD8)", 0xD8, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xDC)", 0xDC, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xE0)", 0xE0, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xE4)", 0xE4, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xE8)", 0xE8, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xEC)", 0xEC, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xF0)", 0xF0, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xF4)", 0xF4, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"u32 RSVD (0xF8)", 0xF8, 32, ACCESS_RW, 0, 0xFFFFFFFF},
		{"SLOT IRQ", 0xFC, 16, ACCESS_RW, 0, 0xFFFF},
		{"HW VERSION", 0xFE, 16, ACCESS_RO, 0x1000, 0},
		{"", 0, 0, 0, 0, 0}
	};
#endif	// __REGINFO__
#endif	// __REGINFO_H__