📄 sdhcmap.h
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// R5 IO Card Status bits (8-bits, R5[15:8])returned in CMD52
#define R5_STAT_ERR (BIT(15) | BIT(14) | BIT(11) | BIT(9) | BIT(8))
#define R5_STAT_CMD_CRC_ERR BIT(15)
#define R5_STAT_ILLEGAL_CMD BIT(14)
#define R5_STAT_CURRENT_STATE (BIT(13)|BIT(12)) // 00=DISabled, 01=CMD, 10=TRN,11=RFU
#define R5_STAT_UNKNOWN_ERR BIT(11)
#define R5_STAT_RFU BIT(10)
#define R5_STAT_INVALID_FUNC BIT(9)
#define R5_STAT_OORANGE BIT(8)
// R6[31:16] = RCA, R6[15:0] are defined here
#define R6_STAT_CMD_CRC_ERR BIT(15)
#define R6_STAT_ILLEGAL_CMD BIT(14)
#define R6_STAT_UNKNOWN_ERR BIT(13)
#define R6_STAT_CURRENT_STATE (BIT(12)|BIT(11)|BIT(10)|BIT(9))
#define R6_STAT_RDY_FOR_DATA BIT(8)
#define R6_STAT_RSVD_7_6 (BIT(7)|BIT(6))
#define R6_STAT_APP_CMD BIT(5)
#define R6_STAT_RSVD_4 BIT(4)
#define R6_STAT_AKE_SEQ_ERR BIT(3)
#define R6_STAT_RSVD_2_0 (BIT(2)|BIT(1)|BIT(0))
// Commands
//
#define CMD_RESET 0
#define CMD_SEND_OCR 1 // used exclusively in MMC
#define CMD_SEND_ALL_CID 2 // R2: R136
#define CMD_SEND_RCA 3 // R1 (MMC) or R6(SDMEM)
#define CMD_SET_DSR 4
#define CMD_IO_SEND_OCR 5 // R4, unique to IO cards
#define CMD_SELECT_CARD 7 // R1, arg=rca[31..16] or 0
#define CMD_SEND_CSD 9 // R2: R136
#define CMD_SEND_CID 10 // R2: R136
#define CMD_STOP_TRANSMISSION 12 // R1b: arg=stuff bits
#define CMD_SEND_STATUS 13 // R1
#define CMD_GO_INACTIVE 15 // None, arg=rca[31..16], stuff[15..0]
#define CMD_SET_BLKLEN 16 // R1, arg=block len[31..0]
#define CMD_RD_SINGLE 17 // R1, arg=block address[31..0]
#define CMD_RD_MULTIPLE 18 // R1, arg=block address[31..0]
#define CMD_WR_SINGLE 24 // R1, arg=block address[31..0]
#define CMD_WR_MULTIPLE 25 // R1, arg=block address[31..0]
#define CMD_SET_WP 28 // R1b, arg=wp address[31..0]
#define CMD_CLR_WP 29 // R1b, arg=wp address[31..0]
#define CMD_SEND_WP 30 // R1, DATA, arg=wp address[31..0]
#define CMD_ERASE_SADDR 32 // R1, arg=block address[31..0]
#define CMD_ERASE_EADDR 33 // R1, arg=block address[31..0]
#define CMD_ERASE_GRP_SADDR 35 // R1, arg=block address[31..0]
#define CMD_ERASE_GRP_EADDR 36 // R1, arg=block address[31..0]
#define CMD_ERASE 38 // R1b, arg=stuff bits[31..0]
#define CMD_IO_RW_DIRECT 52 // R5
#define CMD_IO_RW_EXTENDED 53 // R1, data transfer
#define CMD_APP_CMD 55 // R1, arg=rca[31..16], stuff[15..0]
#define CMD_GEN_CMD 56 // R1, data, arg=stuff[31..1], RD/WR[0]
#define ACMD_SET_BUS_WIDTH 6 // R1, arg=[1..0] = bus width, [31:2] stuff bits
#define ACMD_SEND_STATUS 13 // R1, DATA, arg=stuff bits [31..0]
#define ACMD_SEND_NUM_WR_BLK 22 // R1, DATA, arg=stuff bits [31..0]
#define ACMD_SEND_OCR 41
#define ACMD_SEND_SCR 51 // R1, arg=stuff bits[31..0]
#pragma pack(1)
typedef struct tagCSD2{
unsigned char rsvd; // due to CRC-7 and embedded 'End' bit in the structure
unsigned char version; // b[7:6] = csd_version, b[5:0] = rsvd
unsigned char taac;
unsigned char nsac;
unsigned char tran_speed;
unsigned char ccc;
unsigned char rd_blk_len; // b[7:4]=ccc, b[3:0] = read block len
unsigned char blk_align;
unsigned char c_size;
unsigned char max_rd_curr;
unsigned char max_wr_curr;
unsigned char erase_sz;
unsigned char wp_grp;
unsigned char r2w_factor;
unsigned char wr_blk_len;
unsigned char file_wp;
} CSD_T;
typedef struct tagCID2 { unsigned char rsvd;
unsigned char manuf_id;
unsigned char oem_app_id[2];
unsigned char pdt_name[5];
unsigned char pdt_rev;
unsigned char pdt_sn[4];
unsigned char manuf_date[2];
} CID_T;
typedef struct tagMMC_CID2 { unsigned char rsvd;
unsigned char manuf_id;
unsigned char oem_app_id[2];
unsigned char pdt_name[6];
unsigned char pdt_rev;
unsigned char pdt_sn[4];
unsigned char manuf_date;
} MMC_CID_T;
typedef struct tagSCR2 { unsigned char version;
unsigned char config;
unsigned short rsvd1;
unsigned long rsvd2;
} SCR_T;
#pragma pack()
// these assume that the CSD structure is in native machine endian, for VZ328 (BIG ENDIAN)
#define CSD_STRUCTURE(d) (((d)->version & 0xC0) >> 6)
#define CSD_TAAC(d) ((d)->taac)
#define CSD_NSAC(d) ((d)->nsac)
#define CSD_TRAN_SPEED(d) ((d)->tran_speed)
#define CSD_CCC(d) (((d)->ccc << 4) | (((d)->rd_blk_len & 0xF0) >> 4))
#define CSD_RD_BLK_LEN(d) ((d)->rd_blk_len & 0x0F)
#define CSD_RD_BLK_PARTIAL(d) (((d)->blk_align & 0x80) >> 7)
#define CSD_WR_BLK_MISALIGN(d) (((d)->blk_align & 0x40) >> 6)
#define CSD_RD_BLK_MISALIGN(d) (((d)->blk_align & 0x20) >> 5)
#define CSD_DSR_IMPLEMENTED(d) (((d)->blk_align & 0x10) >> 4)
#define CSD_C_SIZE(d) ((((d)->blk_align & 0x0003) << 10) | \
((d)->c_size << 2) | \
((((d)->max_rd_curr & 0xC0) >> 6) & 0x0003))
#define CSD_MAX_RD_CURR_VMIN(d) (((d)->max_rd_curr & 0x38) >> 3)
#define CSD_MAX_RD_CURR_VMAX(d) ((d)->max_rd_curr & 0x07)
#define CSD_MAX_WR_CURR_VMIN(d) (((d)->max_wr_curr & 0xE0) >> 5)
#define CSD_MAX_WR_CURR_VMAX(d) (((d)->max_wr_curr & 0x1C) >> 2)
#define CSD_C_SIZE_MULT(d) ((((d)->max_wr_curr & 0x03) << 1) | \
(((d)->erase_sz & 0x80) >> 7))
#define CSD_ERASE_BLK_EN(d) (((d)->erase_sz & 0x40) >> 6)
#define MMC_CSD_ERASE_GRP_SZ(d) (((d)->erase_sz & 0x7C) >> 2)
#define MMC_CSD_ERASE_GRP_MULT(d) (((((d)->erase_sz & 0x3) << 3) |\
(((d)->wp_grp & 0xE0) >> 5)) & 0x01F)
#define MMC_CSD_WP_GRP_SZ(d) ((d)->wp_grp & 0x1F)
#define CSD_ERASE_SECTOR_SZ(d) ((((d)->erase_sz & 0x3F) << 1) | \
(((d)->wp_grp & 0x80) >> 7))
#define CSD_WP_GRP_SZ(d) ((d)->wp_grp & 0x007F)
#define CSD_WP_GRP_EN(d) (((d)->r2w_factor & 0x80) >> 7)
#define CSD_R2W_FACTOR(d) (((d)->r2w_factor & 0x1C) >> 2)
#define CSD_WR_BLK_LEN(d) ((((d)->r2w_factor & 0x03) << 2) | \
(((d)->wr_blk_len & 0xC0) >> 6))
#define CSD_WR_BLK_PARTIAL(d) (((d)->wr_blk_len & 0x20) >> 5)
#define CSD_FILE_FMT_GRP(d) (((d)->file_wp & 0x80) >> 7)
#define CSD_COPY_FLAG(d) (((d)->file_wp & 0x40) >> 6)
#define CSD_PERM_WP(d) (((d)->file_wp & 0x20) >> 5)
#define CSD_TEMP_WP(d) (((d)->file_wp & 0x10) >> 4)
#define CSD_FILE_FMT(d) (((d)->file_wp & 0x0C) >> 2)
// SCR bits
#define SCR_STRUCTURE(d) (((d)->version & 0xF0) >> 4)
#define SCR_VERSION(d) ((d)->version & 0x0F)
#define SCR_DATA_AFTER_ERASE(d) (((d)->config & 0x80) >> 7)
#define SCR_SD_SECURITY(d) (((d)->config & 0x70) >> 4)
#define SCR_SD_BUS_WIDTH(d) ((d)->config & 0x0F)
#define SCR_SD_BUS_1BIT BIT(0)
#define SCR_SD_BUS_4BIT BIT(2)
// CCCR
#pragma pack(1)
typedef struct tagCCCR_T2 { unsigned char sdio_rev; // SDIO[b7:b4]/CCCR[b3:b0] spec revision
unsigned char sd_rev; // SD Specification revision
unsigned char ioen; // io function enable
unsigned char iordy; // io function ready
unsigned char ier; // interrrupt enable
unsigned char ipr; // interrupt pending
unsigned char asr; //reset & abort select register
unsigned char bicr; // bus interface control register
unsigned char cap; // card capability
unsigned char cis_ptr[3]; // cis ptr in little endian
unsigned char bsr; // bus suspend
unsigned char fsr; // function select register
unsigned char exr; // Executive Flags Register
unsigned char rdy; // Ready For Write and Read Data (1=rdy)
unsigned char blksz[2]; // I/O Block Size for Fn0
unsigned char rsvd[0xFF-0x11];
} CCCR_T;
#pragma pack()
// CCCR Register addresses
#define CCCR_SDIO_REV 0x00
#define CCCR_SD_REV 0x01
#define CCCR_IO_EN 0x02
#define CCCR_IO_RDY 0x03
#define CCCR_IER 0x04
#define CCCR_IPR 0x05
#define CCCR_ASR 0x06
#define CCCR_BICR 0x07
#define CCCR_CAP 0x08
#define CCCR_CISPTR0 0x09
#define CCCR_CISPTR1 0x0A
#define CCCR_CISPTR2 0x0B
#define CCCR_BSR 0x0C
#define CCCR_FSR 0x0D
#define CCCR_EXR 0x0E
#define CCCR_RDY 0x0F
#define CCCR_FN0_BLKSZ0 0x10
#define CCCR_FN0_BLKSZ1 0x11
// CCCR Reset Abort Function Select
#define CCCR_ASR_RESET BIT(3)
#define CCCR_ASR_SEL (BIT(2)|BIT(1)|BIT(0))
// CCCR Capability Register Bits
#define CCCR_CAP_4BLS BIT(7) // card supports 4-bit mode
#define CCCR_CAP_LSC BIT(6) // card is a low speed card
#define CCCR_CAP_E4MI BIT(5) // 4bit mode interrupt enable
#define CCCR_CAP_S4MI BIT(4) // card supports interrupts in 4-bit mode
#define CCCR_CAP_SBS BIT(3) // card supports bus suspend/resume
#define CCCR_CAP_SRW BIT(2) // card supports read-wait
#define CCCR_CAP_SMB BIT(1) // card supports multiblock
#define CCCR_CAP_SDC BIT(0) // card supports direct commands during multi-byte transfer
// CCCR Bus Suspend/Resume Register Bits
#define CCCR_BSR_DF BIT(7) // Resume Data Flag, 1=more data to transfer after resume
#define CCCR_BSR_BR BIT(1) // rw, BR=bus release request/status
#define CCCR_BSR_BS BIT(0) // ro, BS=bus status, 1=selected fn is using the bus, 0=fn not using
// CCCR Bus Interface Control Register
#define CCCR_BICR_WIDTH (BIT(1)|BIT(0))
#define CCCR_BICR_WIDTH_1 0
#define CCCR_BICR_WIDTH_4 0x02
#pragma pack(1)
// found at offset 0x00n00 for n=1..7 in the CIA - Card
typedef struct tagFBR_T2 { unsigned char id;
unsigned char rsvd0[8];
unsigned char cis_ptr[3];
unsigned char csa_ptr[3];
unsigned char daw; // Data Access Window (FIFO)
unsigned char blksz[2];
unsigned char rsvd1[0xFF-0x11];
} FBR_T;
#pragma pack()
#define FBR_ID 0
#define FBR_ID_CSA_EN BIT(7)
#define FBR_ID_CSA_PRSNT BIT(6)
typedef struct tagTAGVAL {
unsigned long val;
unsigned char tag[32+1];
} TAGVAL_T;
#ifdef __SDREG_C__
TAGVAL_T fbr_id[] = {
{0, "No SDIO"},
{1, "SDIO UART"},
{2, "SDIO Bluetooth (Thin)"},
{3, "SDIO Bluetooth (Complete)"},
{4, "SDIO GPS"},
{5, "SDIO Camera"},
{6, "SDIO PHS"},
{7, "Not assigned - Reserved"},
{8, "Not assigned - Reserved"},
{9, "Not assigned - Reserved"},
{0xA, "Not assigned - Reserved"},
{0xB, "Not assigned - Reserved"},
{0xC, "Not assigned - Reserved"},
{0xD, "Not assigned - Reserved"},
{0xE, "Not assigned - Reserved"},
{0xF, "Not assigned - Reserved"},
{0,""}
};
#else
extern TAGVAL_T fbr_id[];
#endif
#define SDHC_IOCTL_INIT 0x6601
#define SDHC_IOCTL_RESET 0x6602
#define SDHC_IOCTL_GET_CID 0x6603
#define SDHC_IOCTL_GET_CSD 0x6604
#define SDHC_IOCTL_GET_SCR 0x6605
#define SDHC_IOCTL_GET_CCCR 0x6606
#define SDHC_IOCTL_GET_FBR 0x6607
#define SDHC_IOCTL_GET_CIS 0x6608
#define SDHC_IOCTL_GET_WRBLKCNT 0x6609
#define SDHC_IOCTL_GET_STATUS 0x660A
#define SDHC_IOCTL_GET_CARDTYPE 0x660B
#define SDHC_IOCTL_GET_REG 0x660C
#define SDHC_IOCTL_GET_EXT 0x660D
#define SDHC_IOCTL_SET_BLKLEN 0x6610
#define SDHC_IOCTL_SET_WIDTH 0x6611
#define SDHC_IOCTL_SET_SDCLK 0x6612
#define SDHC_IOCTL_SET_DMA 0x6613
#define SDHC_IOCTL_SET_AUTOCMD12 0x6614
#define SDHC_IOCTL_SET_XMODE 0x6615
#define SDHC_IOCTL_READ 0x6620
#define SDHC_IOCTL_WRITE 0x6621
#define SDHC_IOCTL_ABORT 0x6622
#define SDHC_IOCTL_ERASE 0x6623
#define SDHC_IOCTL_READX 0x6624
#define SDHC_IOCTL_WRITEX 0x6625
#define SDHC_IOCTL_IO_READ 0x6640
#define SDHC_IOCTL_IO_WRITE 0x6641
#define SDHC_IOCTL_IO_ABORT 0x6642
#define SDHC_IOCTL_MEMORY_BENCH 0x6650
typedef struct tagSDHC_IOCTL_ARG {
unsigned short cmd;
unsigned long param1; // only used for data read/write
unsigned long param2;
unsigned char *data;
unsigned long len;
int result;
} SDHC_IOCTL_ARG_T;
typedef struct tagCMDTUPLE {
int cmd;
unsigned char name[23+1];
} CMDTUPLE_T;
#if 0
CMDTUPLE_T sdhccmd[] = {
{SDHC_IOCTL_INIT, "init"},
{SDHC_IOCTL_RESET, "reset"},
{SDHC_IOCTL_GET_CID, "cid"},
{SDHC_IOCTL_GET_CSD, "csd"},
{SDHC_IOCTL_GET_SCR, "scr"},
{SDHC_IOCTL_GET_CCCR, "cccr"},
{SDHC_IOCTL_GET_FBR, "fbr"},
{SDHC_IOCTL_GET_CIS, "cis"},
{SDHC_IOCTL_GET_WRBLKCNT, "wrblkcnt"},
{SDHC_IOCTL_GET_STATUS, "status"},
{SDHC_IOCTL_GET_CARDTYPE, "cardtype"},
{SDHC_IOCTL_SET_BLKLEN, "blklen"},
{SDHC_IOCTL_SET_WIDTH, "width"},
{SDHC_IOCTL_SET_SDCLK, "sdclk"},
{SDHC_IOCTL_SET_DMA, "dma"},
{SDHC_IOCTL_SET_AUTOCMD12, "autocmd12"},
{SDHC_IOCTL_READ, "read"},
{SDHC_IOCTL_WRITE, "write"},
{SDHC_IOCTL_ERASE, "erase"},
{SDHC_IOCTL_IO_READ, "ioread"},
{SDHC_IOCTL_IO_WRITE, "iowrite"},
{SDHC_IOCTL_MEMORY_BENCH, "mbench"},
{0,""}
};
#endif
/* end */
#endif // _SDHCMAP_H_
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