📄 sdhcmap.h
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#ifndef _SDHCMAP_H_
#define _SDHCMAP_H_
//#include "type.h"
#include "endian.h"
/* hardware map */
#define REG_u32DMAAddr 0x1100#define REG_u16BlkSize 0x1104#define REG_u16BlkCount 0x1106#define REG_u32Arg 0x1108#define REG_u16TrnsfrMode 0x110c#define REG_u16Cmd 0x110e#define REG_a32Rsp 0x1110#define REG_u8DataPort 0x1120#define REG_a8Rsvd1 0x1121#define REG_u32PrsntState 0x1124#define REG_u8HstCntl 0x1128#define REG_u8PwrCntl 0x1129#define REG_u8BlkGapCntl 0x112a#define REG_u8WkupCntl 0x112b#define REG_u8ClkCntl 0x112c#define REG_u8ClkDiv 0x112d#define REG_u8ToutCntl 0x112e#define REG_u8SwReset 0x112f#define REG_u16NrmIntrStatus 0x1130#define REG_u16ErrIntrStatus 0x1132#define REG_u16NrmIntrStatusEn 0x1134#define REG_u16ErrIntrStatusEn 0x1136#define REG_u16NrmIntrSignalEn 0x1138#define REG_u16ErrIntrSignalEn 0x113a#define REG_u16ACMD12ErrStatus 0x113c#define REG_u16Rsvd2 0x113e#define REG_u32Capabilities 0x1140#define REG_u32CapRsvd 0x1144#define REG_u32MaxCurrCap 0x1148#define REG_u32MaxCurrCapRsvd 0x114c#define REG_u32Rsvd3 0x1150/*REG_u32Rsvd[(0xFC - 0x50) >> 2]*/#define REG_u16SlotIntrStatus 0x11fc#define REG_u16HCVer 0x11fe
typedef volatile struct tagSDHCEXT_T2 { unsigned short u16SDHCCntl;
unsigned short u16FIFOCntl;
unsigned long u32RDFIFOWM;
unsigned long u32WRFIFOWM;
unsigned long u32FIFODMACnt;
unsigned long u32FIFOData;
unsigned long u32CmdCRC;
unsigned short a16DatCRC[4];
unsigned long u32DataCRC2;
unsigned short u16CoreFSM;
unsigned short u16Rsvd;
unsigned long u32Force;
unsigned long u32DataFSM;
unsigned long u32DataToutCnt;
unsigned long u32CSI;
unsigned long u32DSI;
unsigned long a32Rsvd[(0x100-0x38)>>2];
} SDHCEXT_T;
typedef struct tagState {
unsigned short code;
unsigned char name[32];
} CARD_STATE;
#define R1_STATE_NR(x) _card_state[(((x) >> 9) & 0xFUL)].code
#define R5_STATE_NR(x) _io_card_state[(((x) >> 12) & 0x3UL)].code
#define R1_STATE(x) _card_state[(((x) >> 9) & 0xFUL)].name
#define R6_STATE(x) _card_state[(((x) >> 9) & 0xFUL)].name
#define R5_STATE(x) _io_card_state[(((x) >> 12) & 0x3UL)].name
#define R1_STATE_IDLE 0
#define R1_STATE_RDY 1
#define R1_STATE_IDENT 2
#define R1_STATE_STBY 3
#define R1_STATE_TRAN 4
#define R1_STATE_DATA 5
#define R1_STATE_RCV 6
#define R1_STATE_PRG 7
#define R1_STATE_DIS 8
#define R1_STATE_RSVD_9 9
#define R1_STATE_RSVD_A 0x0A
#define R1_STATE_RSVD_B 0x0B
#define R1_STATE_RSVD_C 0x0C
#define R1_STATE_RSVD_D 0x0D
#define R1_STATE_RSVD_E 0x0E
#define R1_STATE_RSVD_F 0x0F
#define R5_STATE_DIS 0
#define R5_STATE_CMD 1
#define R5_STATE_TRN 2
#define R5_STATE_RFU 3
#ifdef __SDHC_CARD_STATE__
CARD_STATE _card_state[] = {
{0, "idle(0)"},
{1, "ready(1)"},
{2, "ident(2)"},
{3, "stby(3)"},
{4, "tran(4)"},
{5, "data(5)"},
{6, "rcv(6)"},
{7, "prg(7)"},
{8, "dis(8)"},
{9, "reserved(9)"},
{10, "reserved(10)"},
{11, "reserved(11)"},
{12, "reserved(12)"},
{13, "reserved(13)"},
{14, "reserved(14)"},
{15, "reserved(15)"},
{0, ""}
};
CARD_STATE _io_card_state[] = {
{0, "DIS(0)"},
{1, "CMD(1)"},
{2, "TRN(2)"},
{3, "RFU(3)"},
{0, ""}
};
#else
extern CARD_STATE _card_state[];
extern CARD_STATE _io_card_state[];
#endif
/*extern volatile unsigned long _sdhc_base;
// register names
#define PTR8(ofs) (*(unsigned char *)(_sdhc_base+(ofs)))
#define PTR16(ofs) (*(unsigned short *)(_sdhc_base+(ofs)))
#define PTR32(ofs) (*(unsigned long *)(_sdhc_base+(ofs)))
#define EPTR16(ofs) (*(unsigned short *)(_sdhc_base-0x100 + (ofs)))
#define EPTR32(ofs) (*(unsigned long *)(_sdhc_base-0x100 + (ofs)))
*/#define DMA PTR32(0)
#define BLKSIZE PTR16(0x04)
#define BLKCOUNT PTR16(0x06)
#define ARGUMENT PTR32(0x08)
#define TRNSFRMODE PTR16(0x0C)
#define CMD PTR16(0x0E)
#define RSP0 PTR32(0x10)
#define RSP1 PTR32(0x14)
#define RSP2 PTR32(0x18)
#define RSP3 PTR32(0x1C)
#define DATAPORT PTR8(0x20)
#define PRSNTSTATE PTR32(0x24)
#define HSTCNTL PTR8(0x28)
#define PWRCNTL PTR8(0x29)
#define BLKGAPCNTL PTR8(0x2A)
#define WKUPCNTL PTR8(0x2B)
#define CLKCNTL PTR8(0x2C)
#define CLKDIV PTR8(0x2D)
#define TOUTCNTL PTR8(0x2E)
#define SWRST PTR8(0x2F)
#define NRMISR PTR16(0x30)
#define ERRISR PTR16(0x32)
#define NRMISREN PTR16(0x34)
#define ERRISREN PTR16(0x36)
#define NRMISIGEN PTR16(0x38)
#define ERRISIGEN PTR16(0x3A)
#define ACMD12ERR PTR16(0x3C)
#define CAPABILITIES PTR32(0x40)
#define MAXCURRCAP PTR32(0x48)
#define SLOTISR PTR16(0xFC)
#define HCVER PTR16(0xFE)
// SDHC Extension Registers
/*#define SDHCCNTL EPTR16(0)
#define FIFOCNTL EPTR16(0x02)
#define RDFIFOWM EPTR32(0x04)
#define WRFIFOWM EPTR32(0x08)
#define FIFODMACNT EPTR32(0x0C)
#define FIFODATADBG EPTR32(0x10)
#define CMDCRC EPTR32(0x14)
#define DAT0CRC EPTR16(0x18)
#define DAT1CRC EPTR16(0x1A)
#define DAT2CRC EPTR16(0x1C)
#define DAT3CRC EPTR16(0x1D)
#define COREFSMSTATE EPTR16(0x20)
#define FORCE EPTR32(0x24)
#define DATAFSMDBG EPTR32(0x28)
#define DATATOUTCNT EPTR32(0x2C)
#define CMDSIDBG EPTR32(0x30)
#define DATSIDBG EPTR32(0x34)
*/// Some bits in SDHC
#define SDHC_HWVER SWAP16(0x1000)
// Some more bits
#define BIT(x) (1 << (x))
#define BIT16(x) SWAP16(BIT(x))
#define BIT32(x) SWAP32(BIT(x))
// Host DMA Boundary and Block Size Register, 0x04
#define DMAR_BLK_SZ_MASK SWAP16(0x0fff)
#define DMAR_BNDRY_MASK SWAP16(0x7000)
// Transfer Mode Register, 16-bit register (0x0C)
#define TMR_DMA_EN BIT16(0)
#define TMR_BLKCNT_EN BIT16(1)
#define TMR_AUTOCMD12_EN BIT16(2)
#define TMR_RD_EN BIT16(4)
#define TMR_MULTI_EN BIT16(5)
// Command Register, 16-bit register (0x0E)
#define CMDR_IDX_MASK SWAP16(0x3F00)
#define CMDR_TYPE_MASK SWAP16(BIT(7) | BIT(6))
#define CMDR_DATA_PRESENT BIT16(5)
#define CMDR_IDX_CHECK_EN BIT16(4)
#define CMDR_CRC_CHECK_EN BIT16(3)
#define CMDR_RSPTYPE_MASK SWAP16(BIT(1) | BIT(0))
#define CMD_IDX(x) SWAP16((x) << 8)
#define CMD_TYPE(x) SWAP16((x) << 6)
#define ABORT 3
#define RESUME 2
#define SUSPEND 1
#define NORMAL 0
#define CMD_RSP(x) SWAP16((x) << 0)
#define R0 0
#define R136 1
#define R48 2
#define R48b 3
// Present State Register Bits, 32-bits (0x24)
#define PSR_CMDLINE_SIGNAL BIT32(24)
#define PSR_DATLINE_SIGNAL SWAP32(BIT(23)|BIT(22)|BIT(21)|BIT(20))
#define PSR_WPSW_PIN BIT32(19)
#define PSR_CARD_DET_PIN BIT32(18)
#define PSR_CARD_STABLE BIT32(17)
#define PSR_CARD_INSERTED BIT32(16)
#define PSR_BUF_RDEN BIT32(11)
#define PSR_BUF_WREN BIT32(10)
#define PSR_RD_ACTIVE BIT32(9)
#define PSR_WR_ACTIVE BIT32(8)
#define PSR_DATLINE_ACTIVE BIT32(2)
#define PSR_INHIBIT_DAT BIT32(1)
#define PSR_INHIBIT_CMD BIT32(0)
// Host Control , 8-bit (0x28)
#define HCR_HISPEED_EN BIT(2)
#define HCR_TRANS_WIDTH BIT(1)
#define HCR_LED_EN BIT(0)
// Power Control, 8-bit (0x29)
#define PCR_SDBUS_VMASK (BIT(3) | BIT(2) | BIT(1))
#define PCR_SDBUS_PWRON BIT(0)
#define PCR_SDBUS_V3_3 0x0E
#define PCR_SDBUS_V3_0 0x0C
#define PCR_SDBUS_V1_8 0x0A
// Block GAP Register Bits, 8-bit (0x2A)
#define BLKGAP_INTR_REQ BIT(3)
#define BLKGAP_RDWAIT_CNTL BIT(2)
#define BLKGAP_CONT_REQ BIT(1)
#define BLKGAP_STOP_REQ BIT(0)
// Clock Control Register, 8-bit register (0x2C)
#define CCR_SDCLK_EN BIT(2)
#define CCR_ICLK_STABLE BIT(1)
#define CCR_ICLK_EN BIT(0)
// Wakeup Control Register, 8-bit (0x2E)
#define WKR_CARD_REMOVAL BIT(2)
#define WKR_CARD_INSERT BIT(1)
#define WKR_CARD_IRQ BIT(0)
// Software Reset Register bits, 8-bit (0x2F)
#define SW_RESET_DATA BIT(2)
#define SW_RESET_CMD BIT(1)
#define SW_RESET_ALL BIT(0)
// Normal Interrupt Status Register (0x30)
// Bits are common between Status, Enable, and Signal Enable registers
#define INTR_ERR BIT16(15)
#define INTR_CARD BIT16(8)
#define INTR_CARD_REMOVAL BIT16(7)
#define INTR_CARD_INSERTION BIT16(6)
#define INTR_BUF_RD_RDY BIT16(5)
#define INTR_BUF_WR_RDY BIT16(4)
#define INTR_DMA BIT16(3)
#define INTR_BLK_GAP BIT16(2)
#define INTR_DAT_COMPLETE BIT16(1)
#define INTR_CMD_COMPLETE BIT16(0)
// Error Interrupt Status Register (0x32)
// Bits are common between Status, Enable, and Signal Enable registers
#define EINTR_VS_BLKSZ_ERR BIT16(14)
#define EINTR_VS_DAT_CONFLICT BIT16(13)
#define EINTR_VS_RSP_DIR BIT16(12)
#define EINTR_AUTOCMD12 BIT16(8)
#define EINTR_CURR_LIMIT BIT16(7)
#define EINTR_DAT_END BIT16(6)
#define EINTR_DAT_CRC BIT16(5)
#define EINTR_DAT_TOUT BIT16(4)
#define EINTR_CMD_IDX BIT16(3)
#define EINTR_CMD_END BIT16(2)
#define EINTR_CMD_CRC BIT16(1)
#define EINTR_CMD_TOUT BIT16(0)
// Capabilities Register, 32-bits (0x40)
#define CAP_SDBUS_V3_3 BIT32(26)
#define CAP_SDBUS_V3_0 BIT32(25)
#define CAP_SDBUS_V1_8 BIT32(24)
#define CAP_SUSPEND_RESUME BIT32(23)
#define CAP_DMA_SUPPORT BIT32(22)
#define CAP_HI_SPEED BIT32(21)
#define CAP_MAX_BLK_LEN SWAP32((BIT(17) | BIT(16)))
#define CAP_BCLK_FREQ SWAP32(BIT(13) | BIT(12) | \
BIT(11) | BIT(10) | \
BIT(9) | BIT(8))
#define CAP_TOUT_CLK_UNIT BIT32(7)
#define CAP_TOUT_CLK_FREQ SWAP32(BIT(5) | BIT(4) | BIT(3) | \
BIT(2) | BIT(1) | BIT(0))
/**************** card related ***************************/
/* R1_sd status from cmd13 */
#define R1_STAT_OORANGE BIT(31) // e r x
#define R1_STAT_ADDR_ERR BIT(30) // e r
#define R1_STAT_BLK_LEN_ERR BIT(29) // e r
#define R1_STAT_ERASE_SEQ_ERR BIT(28) // e r
#define R1_STAT_ERASE_PARAM_ERR BIT(27) // e r x
#define R1_STAT_WP_VIOLATION BIT(26) // e r x
#define R1_STAT_CARD_IS_LOCKED BIT(25) // s x
#define R1_STAT_LOCK_UNLOCK_FAILED BIT(24) // e r x
#define R1_STAT_CMD_CRC_ERR BIT(23) // e r
#define R1_STAT_ILLEGAL_CMD BIT(22) // e r
#define R1_STAT_CARD_ECC_FAILED BIT(21) // e r x
#define R1_STAT_CC_ERR BIT(20) // e r x
#define R1_STAT_UNKNOWN_ERR BIT(19) // e r x
#define R1_STAT_RSVD_18_17 (BIT(18)|BIT(17))
#define R1_STAT_CIDCSD_OVWRITE BIT(16) // e r x
#define R1_STAT_WP_ERASE_SKIP BIT(15) // s x
#define R1_STAT_CARD_ECC_DISAB BIT(14) // s x
#define R1_STAT_ERASE_RST BIT(13) // s r
#define R1_STAT_CURRENT_STATE (BIT(12)|BIT(11)|BIT(10)|BIT(9)) // s x
#define R1_STAT_RDY_FOR_DATA BIT(8) // s x
#define R1_STAT_RSVD_7_6 (BIT(7)|BIT(6))
#define R1_STAT_APP_CMD BIT(5) // s r
#define R1_STAT_RSVD_4 BIT(4)
#define R1_STAT_AKE_SEQ_ERR BIT(3) // e r
#define R1_STAT_RSVD_2_0 (BIT(2)|BIT(1)|BIT(0))
#define R1_STAT_ERR (R1_STAT_CMD_CRC_ERR | R1_STAT_ILLEGAL_CMD | \
R1_STAT_CC_ERR | R1_STAT_UNKNOWN_ERR)
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