fpusb.c

CY68013 芯片USB开发固件程序。

#pragma NOIV               // Do not generate interrupt vectors

#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h"            // SYNCDELAY macro

extern BOOL GotSUD;             // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;

BYTE Configuration;             // Current configuration
BYTE AlternateSetting;          // Alternate settings

//-----------------------------------------------------------------------------
// Constants
//-----------------------------------------------------------------------------
#define	VR_UPLOAD           0xc0
#define VR_DOWNLOAD         0x40

#define VR_ANCHOR_DLD       0xa0 // handled by core
#define VR_SEND_COMMAND     0xa2 // Send Command
#define VR_RESET_FIFO       0xa3 // Get Image

//-----------------------------------------------------------------------------
// Task Dispatcher hooks
//   The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------

sbit PA0 = IOA ^ 0;
sbit PA1 = IOA ^ 1;
sbit PA2 = IOA ^ 2;
sbit PA3 = IOA ^ 3;
sbit PA4 = IOA ^ 4;
sbit PA5 = IOA ^ 5;
sbit PA6 = IOA ^ 6;
sbit PA7 = IOA ^ 7;

bit x;

void TD_Init(void)              // Called once at startup
{
  // set the CPU clock to 48MHz
  CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
	
  // set the CPU clock to 24MHz
  // CPUCS = 0x0A ;
  // Registers which require a synchronization delay, see section 15.14
  // FIFORESET        FIFOPINPOLAR
  // INPKTEND         OUTPKTEND
  // EPxBCH:L         REVCTL
  // GPIFTCB3         GPIFTCB2
  // GPIFTCB1         GPIFTCB0
  // EPxFIFOPFH:L     EPxAUTOINLENH:L
  // EPxFIFOCFG       EPxGPIFFLGSEL
  // PINFLAGSxx       EPxFIFOIRQ
  // EPxFIFOIE        GPIFIRQ
  // GPIFIE           GPIFADRH:L
  // UDMACRCH:L       EPxGPIFTRIG
  // GPIFTRIG
  
  // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
  //      ...these have been replaced by GPIFTC[B3:B0] registers

  // default: all endpoints have their VALID bit set
  // default: TYPE1 = 1 and TYPE0 = 0 --> BULK  
  // default: EP2 and EP4 DIR bits are 0 (OUT direction)
  // default: EP6 and EP8 DIR bits are 1 (IN direction)
  // default: EP2, EP4, EP6, and EP8 are double buffered

  REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1
  SYNCDELAY;
  
  
  // we are just using the default values, yes this is not necessary...
  EP1OUTCFG = 0xA0;
  EP1INCFG = 0xA0;
  SYNCDELAY;                    // see TRM section 15.14
  EP2CFG = 0xA2;
  SYNCDELAY;                    // 
  EP4CFG = 0xA0;				//0xA0;
  SYNCDELAY;                    // 
  EP6CFG = 0xE2;
  SYNCDELAY;                    // 
  EP8CFG = 0xE0;
  SYNCDELAY;                    // 

  // out endpoints do not come up armed
  
  // since the defaults are double buffered we must write dummy byte counts twice
  EP2BCL = 0x80;                // arm EP2OUT by writing byte count w/skip.
  SYNCDELAY;                    // 
  EP4BCL = 0x80;    
  SYNCDELAY;                    // 
  EP2BCL = 0x80;                // arm EP4OUT by writing byte count w/skip.
  SYNCDELAY;                    // 
  EP4BCL = 0x80;    
  SYNCDELAY;                    // 
     

  FIFORESET = 0x80; // reset all FIFOs
  SYNCDELAY;
  FIFORESET = 0x02;
  SYNCDELAY;
  FIFORESET = 0x04;
  SYNCDELAY;
  FIFORESET = 0x06;
  SYNCDELAY;
  FIFORESET = 0x08;
  SYNCDELAY;
  FIFORESET = 0x00;
  SYNCDELAY;

  IFCONFIG = 0xcb;   // this defines the external interface to be the following:
                     // use IFCLK pin driven by internal logic, clk frequency is 48MHz
                     // use slave FIFO interface pins driven async by external master
  SYNCDELAY;

//-------------------------设置端点6\8为自动输入模式--------------------

  EP6AUTOINLENH = 02;  // EP6 auto in length: 512  //512:02  64:00
  SYNCDELAY;
  EP6AUTOINLENL = 00;							 //512:00   64:64
  SYNCDELAY;

  EP8AUTOINLENH = 02;  // EP8 auto in length: 512  //512:02  64:00
  SYNCDELAY;
  EP8AUTOINLENL = 00;							 //512:00   64:64
  SYNCDELAY;

  //-----------------------设置端点4为CPU commit模式----------------------
  EP2FIFOCFG = 0x00; // this lets the EP4 auto=0 commit OUT packets,
                     // and sets the slave FIFO data interface to 8-bits
  SYNCDELAY;
  
  EP4FIFOCFG = 0x00; // this lets the EP4 auto=0 commit OUT packets,
                     // and sets the slave FIFO data interface to 8-bits
  SYNCDELAY;

  OUTPKTEND = 0x84; // Arm both EP4 buffers to “prime the pump”
  SYNCDELAY;
  OUTPKTEND = 0x84;
  SYNCDELAY;

  

  EP6FIFOCFG = 0x08; // this lets the EP6 auto commit IN packets,
                     // and sets the slave FIFO data interface to 8-bits
  SYNCDELAY;

  EP8FIFOCFG = 0x08; // this lets the EP8 auto commit IN packets,
                     // and sets the slave FIFO data interface to 8-bits
  SYNCDELAY;


//-----------------------------------------------------------------------------

  PINFLAGSAB = 0x00; // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
                     // FLAGB as full flag, as pointed to by FIFOADR[1:0]
  SYNCDELAY;

  PINFLAGSCD = 0x00; // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
  SYNCDELAY;

  PORTACFG = 0x00;   // used PA7/FLAGD  a PORTA pin  ,no as a FIFO flag SLCS
  SYNCDELAY;

  FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low
  SYNCDELAY;
  
   if (EZUSB_HIGHSPEED())
   {
      EP6AUTOINLENH = 02;  // EP6 auto in length: 512  //512:02  64:00
 	  SYNCDELAY;
      EP6AUTOINLENL = 00;							 //512:00   64:64
      SYNCDELAY;

      EP8AUTOINLENH = 02;  // EP8 auto in length: 512  //512:02  64:00
      SYNCDELAY;
      EP8AUTOINLENL = 00;							 //512:00   64:64
      SYNCDELAY;
	  PA7=0;
   }
   else
   {
      EP6AUTOINLENH = 00;  // EP6 auto in length:  64:00
      SYNCDELAY;
      EP6AUTOINLENL = 64;							 //64:64
      SYNCDELAY;

      EP8AUTOINLENH = 00;  // EP8 auto in length:  //00
      SYNCDELAY;
      EP8AUTOINLENL = 64;							 //64
      SYNCDELAY;
	  PA7=1;
   }



  OEA = 0x8b;
  IOA &= 0x88;
  x=0;    
}

void TD_Poll(void)              // Called repeatedly while the device is idle
{
	
	if( (!x)&& (EZUSB_HIGHSPEED()) )
	 {EP6AUTOINLENH = 02;  // EP6 auto in length: 512  //512:02  64:00
 	  SYNCDELAY;
      EP6AUTOINLENL = 00;							 //512:00   64:64
      SYNCDELAY;

      EP8AUTOINLENH = 02;  // EP8 auto in length: 512  //512:02  64:00
      SYNCDELAY;
      EP8AUTOINLENL = 00;							 //512:00   64:64
      SYNCDELAY;
	  PA7=0;
	  x=1;
	 }
	if( (x)&& (!EZUSB_HIGHSPEED()) )
	 {EP6AUTOINLENH = 00;  // EP6 auto in length: 512  //512:02  64:00
 	  SYNCDELAY;
      EP6AUTOINLENL = 64;							 //512:00   64:64
      SYNCDELAY;

      EP8AUTOINLENH = 00;  // EP8 auto in length: 512  //512:02  64:00
      SYNCDELAY;
      EP8AUTOINLENL = 64;							 //512:00   64:64
      SYNCDELAY;
	  PA7=1;
	  x=0;
	 }


 	if( !( EP2468STAT & 0x04 ) )
	     { // EP4EF=0 when FIFO NOT empty, host sent packet
          
		  OUTPKTEND = 0x04; // SKIP=0, pass buffer on to master
          SYNCDELAY;
		  
		  PA7=!PA7;
  	     }

}

BOOL TD_Suspend(void)          // Called before the device goes into suspend mode
{  
   return(TRUE);
}

BOOL TD_Resume(void)          // Called after the device resumes
{
   
	return(TRUE);
}

//-----------------------------------------------------------------------------
// Device Request hooks
//   The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------

BOOL DR_GetDescriptor(void)
{
   return(TRUE);
}

BOOL DR_SetConfiguration(void)   // Called when a Set Configuration command is received
{
   Configuration = SETUPDAT[2];
   return(TRUE);            // Handled by user code
}

BOOL DR_GetConfiguration(void)   // Called when a Get Configuration command is received
{
   EP0BUF[0] = Configuration;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);            // Handled by user code
}

BOOL DR_SetInterface(void)       // Called when a Set Interface command is received
{
   AlternateSetting = SETUPDAT[2];
   return(TRUE);            // Handled by user code
}

BOOL DR_GetInterface(void)       // Called when a Set Interface command is received
{
   EP0BUF[0] = AlternateSetting;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);            // Handled by user code
}

BOOL DR_GetStatus(void)
{
   return(TRUE);
}

BOOL DR_ClearFeature(void)
{
   return(TRUE);
}

BOOL DR_SetFeature(void)
{
   return(TRUE);
}

BOOL DR_VendorCmnd(void)
{
    switch(SETUPDAT[1])
    {
		case VR_SEND_COMMAND:
			PA0 = SETUPDAT[2] & 1;
			PA1 = (SETUPDAT[2] >> 1) & 1;

			PA3 = 0;
			PA3 = 1;

		   break;
		case VR_RESET_FIFO:
            

			FIFORESET = 0x80; // reset all FIFOs
            SYNCDELAY;
            FIFORESET = 0x02;
            SYNCDELAY;
            FIFORESET = 0x04;
            SYNCDELAY;
            FIFORESET = 0x06;
            SYNCDELAY;
            FIFORESET = 0x08;
            SYNCDELAY;
            FIFORESET = 0x00;
            SYNCDELAY;

            break;
    }

	return(FALSE); // no error; command handled OK
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
   GotSUD = TRUE;            // Set flag
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUDAV;         // Clear SUDAV IRQ
}

// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUTOK;         // Clear SUTOK IRQ
}

void ISR_Sof(void) interrupt 0
{
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSOF;            // Clear SOF IRQ
}

void ISR_Ures(void) interrupt 0
{
   if (EZUSB_HIGHSPEED())
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }
   
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmURES;         // Clear URES IRQ
}

void ISR_Susp(void) interrupt 0
{
   Sleep = TRUE;
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUSP;
   
}

void ISR_Highspeed(void) interrupt 0
{
   if (EZUSB_HIGHSPEED())
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;

   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
 
    }

   EZUSB_IRQ_CLEAR();
   USBIRQ = bmHSGRANT;
   
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
void ISR_Ep2inout(void) interrupt 0
{
}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}