sect30.inc

针对日本瑞莎单片机r8c/23系列开发的LIN网络开发编程

;*******************************************************************************
;
; C Compiler for R8C/Tiny, M16C/60,30,20,10
; Copyright(C) 1999(2000-2004). Renesas Technology Corp.
; and Renesas Solutions Corp., All rights reserved.
;
;
; Written by T.Aoyama
;
; sect30.inc     : section definition
; This program is applicable when using the basic I/O library
;
; $Id: sect30.inc,v 1.23.4.6 2004/10/29 14:06:39 simomura Exp $
;
;******************************************************************************
;
;---------------------------------------------------------------------
; STACK SIZE definition
;---------------------------------------------------------------------
STACKSIZE   .equ  100h
;
;---------------------------------------------------------------------
; INTERRUPT STACK SIZE definition
;---------------------------------------------------------------------
ISTACKSIZE  .equ  100h
;
;---------------------------------------------------------------------
; INTERRUPT VECTOR ADDRESS  definition
;---------------------------------------------------------------------
;VECTOR_ADR  .equ  0fedch
VECTOR_ADR  .equ  0fe00h
;
;====================================================================
; Initialize Macro declaration
;---------------------------------------------------------------------
N_BZERO .macro  TOP_ ,SECT_
    mov.b   #00H, R0L
    mov.w   #(TOP_ & 0FFFFH), A1
    mov.w   #sizeof SECT_ , R3
    sstr.b
    .endm
;
N_BCOPY .macro  FROM_,TO_,SECT_
    mov.w   #(FROM_ & 0FFFFH),A0
    mov.b   #(FROM_ >>16),R1H
    mov.w   #TO_ ,A1
    mov.w   #sizeof SECT_ , R3
    smovf.b
    .endm
;
;---------------------------------------------------------------
;
;  Arrangement of section
;
;---------------------------------------------------------------
; Near RAM data area
;---------------------------------------------------------------
; SBDATA area
   .section data_SE,DATA
   .org  400H
data_SE_top:

   .section bss_SE,DATA,ALIGN
bss_SE_top:

   .section data_SO,DATA
data_SO_top:

   .section bss_SO,DATA
bss_SO_top:

; near RAM area
   .section data_NE,DATA,ALIGN
data_NE_top:

   .section bss_NE,DATA,ALIGN
bss_NE_top:

   .section data_NO,DATA
data_NO_top:

   .section bss_NO,DATA
bss_NO_top:

;---------------------------------------------------------------
; Stack area
;---------------------------------------------------------------
   .section stack,DATA,ALIGN
   .blkb STACKSIZE
stack_top:

   .blkb ISTACKSIZE
istack_top:

;---------------------------------------------------------------
; Near ROM data area
;---------------------------------------------------------------
   .section rom_NE,ROMDATA
   .org     04000H
rom_NE_top:

   .section rom_NO,ROMDATA
rom_NO_top:

;---------------------------------------------------------------
; Initial data of 'data' section
;---------------------------------------------------------------
   .section data_SEI,ROMDATA,ALIGN
data_SEI_top:

   .section data_SOI,ROMDATA
data_SOI_top:

   .section data_NEI,ROMDATA,ALIGN
data_NEI_top:

   .section data_NOI,ROMDATA
data_NOI_top:

;---------------------------------------------------------------
; Switch Table Section
;---------------------------------------------------------------
   .section        switch_table,ROMDATA
switch_table_top:

;---------------------------------------------------------------
; code area
;---------------------------------------------------------------
;
   .section program,CODE,ALIGN

   .section boot_code,CODE,ALIGN

;---------------------------------------------------------------
; variable vector section
;---------------------------------------------------------------
   .glb  _LIN_Break_ISR
   .glb  _LIN_Xmt_ISR
   .glb  _LIN_Rcv_ISR
   .glb  _LIN_Schedule_ISR

   .section vector,ROMDATA ; variable vector table
   .org  VECTOR_ADR

   .lword   dummy_int      ; BRK (vector 0)
   .lword   dummy_int      ; Reserved (vector 1)
   .lword   dummy_int      ; Reserved (vector 2)
   .lword   dummy_int      ; CAN0 Wake-Up (vector 3)
   .lword   dummy_int      ; CAN0 Successful Receive (vector 4)
   .lword   dummy_int      ; CAN0 Successful Transmit (vector 5)
   .lword   dummy_int      ; CAN0 Error (vector 6)
   .lword   dummy_int      ; Reserved (vector 7)
   .lword   dummy_int      ; Timer RD Channel 1 (vector 8)
   .lword   dummy_int      ; Timer RD Channel 2 (vector 9)
   .lword   dummy_int      ; Timer RE (vector 10)
   .lword   dummy_int      ; Reserved (vector 11)
   .lword   dummy_int      ; Reserved (vector 12)
   .lword   dummy_int      ; Key Input (vector 13)
   .lword   dummy_int      ; AD Conversion (vector 14)
   .lword   dummy_int      ; SSU/IIC (vector 15)
   .lword   dummy_int      ; Reserved (vector 16)
   .lword   _LIN_Xmt_ISR   ; UART0 Transmit (vector 17)
   .lword   _LIN_Rcv_ISR   ; UART0 Receive (vector 18)
   .lword   dummy_int      ; UART1 Transmit (vector 19)
   .lword   dummy_int      ; UART1 Receive (vector 20)
   .lword   dummy_int      ; INT2 (vector 21)
   .lword   _LIN_Break_ISR ; Timer RA (vector 22)
   .lword   dummy_int      ; Reserved (vector 23)
   .lword   _LIN_Schedule_ISR ; Timer RB (vector 24)
   .lword   dummy_int      ; INT1 (vector 25)
   .lword   dummy_int      ; INT3 (vector 26)
   .lword   dummy_int      ; Reserved (vector 27)
   .lword   dummy_int      ; Reserved (vector 28)
   .lword   dummy_int      ; INT0 (vector 29)
   .lword   dummy_int      ; Reserved (vector 30)
   .lword   dummy_int      ; Reserved (vector 31)
   .lword   dummy_int      ; vector 32
   .lword   dummy_int      ; vector 33
   .lword   dummy_int      ; vector 34
   .lword   dummy_int      ; vector 35
   .lword   dummy_int      ; vector 36
   .lword   dummy_int      ; vector 37
   .lword   dummy_int      ; vector 38
   .lword   dummy_int      ; vector 39
   .lword   dummy_int      ; vector 40
   .lword   dummy_int      ; vector 41
   .lword   dummy_int      ; vector 42
   .lword   dummy_int      ; vector 43
   .lword   dummy_int      ; vector 44
   .lword   dummy_int      ; vector 45
   .lword   dummy_int      ; vector 46
   .lword   dummy_int      ; vector 47
   .lword   dummy_int      ; vector 48
   .lword   dummy_int      ; vector 49
   .lword   dummy_int      ; vector 50
   .lword   dummy_int      ; vector 51
   .lword   dummy_int      ; vector 52
   .lword   dummy_int      ; vector 53
   .lword   dummy_int      ; vector 54
   .lword   dummy_int      ; vector 55
   .lword   dummy_int      ; vector 56
   .lword   dummy_int      ; vector 57
   .lword   dummy_int      ; vector 58
   .lword   dummy_int      ; vector 59
   .lword   dummy_int      ; vector 60
   .lword   dummy_int      ; vector 61
   .lword   dummy_int      ; vector 62
   .lword   dummy_int      ; vector 63

;===============================================================
; fixed vector section
;---------------------------------------------------------------
   .section fvector,ROMDATA      ; fixed vector table
;  .org  0ffdcH
;UDI:
;  .lword   dummy_int
;OVER_FLOW:
;  .lword   dummy_int
;BRKI:
;  .lword   dummy_int
;ADDRESS_MATCH:
;  .lword   dummy_int
;SINGLE_STEP:
;  .lword   dummy_int
;WDT:
;  .lword   dummy_int
;RESERVED:
;  .lword   dummy_int
;RESERVED:
;  .lword   dummy_int
   .org  0fffcH
RESET:
   .lword   start
   ;
   ; ID code check function
   ; .id "CodeChk"
   ;
   ; option function select register
   ;
   .ofsreg  0FFH

;****************************************************************************
;
;  C Compiler for R8C/Tiny, M16C/60,30,20,10
; Copyright(C) 1999(2000-2004). Renesas Technology Corp.
; and Renesas Solutions Corp., All rights reserved.
;
;****************************************************************************