sfr_r823.h

针对日本瑞莎单片机r8c/23 开发的LIN网络通讯程序包括主节点和从节点

union	byte_def	pm1_addr;
#define		pm1			pm1_addr.byte

#define		pm12		pm1_addr.bit.b2			/* WDT interrupt/reset switch bit */

/*------------------------------------------------------
  System clock control register0
------------------------------------------------------*/
union	byte_def	cm0_addr;
#define		cm0			cm0_addr.byte

#define		cm02		cm0_addr.bit.b2			/* WAIT peripheral function clock stop bit */
#define		cm05		cm0_addr.bit.b5			/* Xin clock (Xin-Xout) stop bit */
#define		cm06		cm0_addr.bit.b6			/* System clock division select bit0 */

/*------------------------------------------------------
  System clock control register1
------------------------------------------------------*/
union	byte_def	cm1_addr;
#define		cm1			cm1_addr.byte

#define		cm10		cm1_addr.bit.b0			/* All clock stop control bit */
#define		cm13		cm1_addr.bit.b3			/* Port Xin-Xout switch bit */
#define		cm14		cm1_addr.bit.b4			/* Low-speed on-chip oscillation stop bit */
#define		cm15		cm1_addr.bit.b5			/* Xin-Xout drive capacity select bit */
#define		cm16		cm1_addr.bit.b6			/* System clock division select bit1 */
#define		cm17		cm1_addr.bit.b7			/* System clock division select bit1 */

/*------------------------------------------------------
  Address match interrupt enable register
------------------------------------------------------*/
union	byte_def	aier_addr;
#define		aier		aier_addr.byte

#define		aier0		aier_addr.bit.b0		/* Address match interrupt 0 enable bit */
#define		aier1		aier_addr.bit.b1		/* Address match interrupt 1 enable bit */

/*------------------------------------------------------
  Protect register
------------------------------------------------------*/
union	byte_def	prcr_addr;
#define		prcr		prcr_addr.byte

#define		prc0		prcr_addr.bit.b0		/* Protect bit0 */
#define		prc1		prcr_addr.bit.b1		/* Protect bit1 */
#define		prc2		prcr_addr.bit.b2		/* Protect bit2 */
#define		prc3		prcr_addr.bit.b3		/* Protect bit3 */

/*------------------------------------------------------
  Oscillation stop detection register
------------------------------------------------------*/
union	byte_def	ocd_addr;
#define		ocd			ocd_addr.byte

#define		ocd0		ocd_addr.bit.b0			/* Oscillation stop detection enable bit */
#define		ocd1		ocd_addr.bit.b1			/* Oscillation stop detection interrupt enable bit */
#define		ocd2		ocd_addr.bit.b2			/* System clock select bit */
#define		ocd3		ocd_addr.bit.b3			/* Clock monitor bit */

/*------------------------------------------------------
  Watchdog timer reset register
------------------------------------------------------*/
union	byte_def	wdtr_addr;
#define		wdtr		wdtr_addr.byte

/*------------------------------------------------------
  Watchdog timer start register
------------------------------------------------------*/
union	byte_def	wdts_addr;
#define		wdts		wdts_addr.byte

/*------------------------------------------------------
  Watchdog timer control register
------------------------------------------------------*/
union	byte_def	wdc_addr;
#define		wdc			wdc_addr.byte

#define		wdc7		wdc_addr.bit.b7			/* Prescaler select bit */

/*------------------------------------------------------
  Count source protection mode register
------------------------------------------------------*/
union	byte_def	cspr_addr;
#define		cspr		cspr_addr.byte
#define		cspro		cspr_addr.bit.b7		/* Count source protection mode select bit */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 0
------------------------------------------------------*/
union	byte_def	fra0_addr;
#define		fra0		fra0_addr.byte

#define		fra00		fra0_addr.bit.b0		/* High-speed on-chip oscillator enable bit */
#define		fra01		fra0_addr.bit.b1		/* High-speed on-chip oscillator select bit */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 1
------------------------------------------------------*/
union	byte_def	fra1_addr;
#define		fra1		fra1_addr.byte

/*------------------------------------------------------
  High-speed on-chip oscillator control register 2
------------------------------------------------------*/
union	byte_def	fra2_addr;
#define		fra2		fra2_addr.byte

#define		fra20		fra2_addr.bit.b0		/* High-speed on-chip oscillator frequency switching bit */
#define		fra21		fra2_addr.bit.b1		/* High-speed on-chip oscillator frequency switching bit */
#define		fra22		fra2_addr.bit.b2		/* High-speed on-chip oscillator frequency switching bit */

/*------------------------------------------------------
  Voltage detection register 1
------------------------------------------------------*/
union	byte_def	vca1_addr;
#define		vca1		vca1_addr.byte

#define		vca13		vca1_addr.bit.b3		/* Voltage detection 2 signal monitor flag */

/*------------------------------------------------------
  Voltage detection register 2
------------------------------------------------------*/
union	byte_def	vca2_addr;
#define		vca2		vca2_addr.byte

#define		vca26		vca2_addr.bit.b6		/* Voltage detection 1 enable bit */
#define		vca27		vca2_addr.bit.b7		/* Voltage detection 2 enable bit */

/*------------------------------------------------------
  Voltage monitor 1 circuit control register
------------------------------------------------------*/
union	byte_def	vw1c_addr;
#define		vw1c		vw1c_addr.byte

#define		vw1c0		vw1c_addr.bit.b0		/* Voltage monitor 1 interrupt / reset enable bit */
#define		vw1c1		vw1c_addr.bit.b1		/* Voltage Monitor 1 digital filter disable mode select bit */
#define		vw1c2		vw1c_addr.bit.b2		/* Voltage change detection flag */
#define		vw1f0		vw1c_addr.bit.b4		/* Sampling clock select bit */
#define		vw1f1		vw1c_addr.bit.b5		/* Sampling clock select bit */
#define		vw1c6		vw1c_addr.bit.b6		/* Voltage monitor 1 circuit mode select bit */
#define		vw1c7		vw1c_addr.bit.b7		/* Voltage monitor 1 interrupt / reset generation condition select bit */

/*------------------------------------------------------
  Voltage monitor 2 circuit control register
------------------------------------------------------*/
union	byte_def	vw2c_addr;
#define		vw2c		vw2c_addr.byte

#define		vw2c0		vw2c_addr.bit.b0		/* Voltage monitor 2 interrupt / reset enable bit */
#define		vw2c1		vw2c_addr.bit.b1		/* Voltage monitor 2 digital filter disabled mode select bit */
#define		vw2c2		vw2c_addr.bit.b2		/* Voltage change detection flag */
#define		vw2c3		vw2c_addr.bit.b3		/* WDT Detection Flag */
#define		vw2f0		vw2c_addr.bit.b4		/* Sampling clock select bit */
#define		vw2f1		vw2c_addr.bit.b5		/* Sampling clock select bit */
#define		vw2c6		vw2c_addr.bit.b6		/* Voltage monitor 2 circuit mode select bit */
#define		vw2c7		vw2c_addr.bit.b7		/* Voltage monitor 2 interrupt / reset generation condition select bit */

/*------------------------------------------------------
  UART0 bit rate register
------------------------------------------------------*/
union	byte_def	u0brg_addr;
#define		u0brg		u0brg_addr.byte

/*------------------------------------------------------
  UART1 bit rate register
------------------------------------------------------*/
union	byte_def	u1brg_addr;
#define		u1brg		u1brg_addr.byte

/*------------------------------------------------------
  SS control register H
------------------------------------------------------*/
union	byte_def	sscrh_addr;
#define		sscrh		sscrh_addr.byte

#define		cks0_sscrh	sscrh_addr.bit.b0		/* Transfer clock rate select bit */
#define		cks1_sscrh	sscrh_addr.bit.b1		/* Transfer clock rate select bit */
#define		cks2_sscrh	sscrh_addr.bit.b2		/* Transfer clock rate select bit */
#define		mss_sscrh	sscrh_addr.bit.b5		/* Master/Slave device select bit */
#define		rsstp_sscrh	sscrh_addr.bit.b6		/* Receive single stop bit */

/*------------------------------------------------------
  SS control register L
------------------------------------------------------*/
union	byte_def	sscrl_addr;
#define		sscrl		sscrl_addr.byte

#define		sres_sscrl	sscrl_addr.bit.b1		/* Clock synchronous serial I/O with chip select control part reset bit */
#define		solp_sscrl	sscrl_addr.bit.b4		/* SOL write protect bit */
#define		sol_sscrl	sscrl_addr.bit.b5		/* Serial data output value setting bit */

/*------------------------------------------------------
  SS mode register
------------------------------------------------------*/
union	byte_def	ssmr_addr;
#define		ssmr		ssmr_addr.byte

#define		bc0_ssmr	ssmr_addr.bit.b0		/* Bit counter 2 to 0*/
#define		bc1_ssmr	ssmr_addr.bit.b1		/* Bit counter 2 to 0*/
#define		bc2_ssmr	ssmr_addr.bit.b2		/* Bit counter 2 to 0*/
#define		cphs_ssmr	ssmr_addr.bit.b5		/* SSCK clock phase select bit */
#define		cpos_ssmr	ssmr_addr.bit.b6		/* SSCK clock polarity select bit */
#define		mls_ssmr	ssmr_addr.bit.b7		/* MSB first/ LSB first select bit */

/*------------------------------------------------------
  SS enable register 
------------------------------------------------------*/
union	byte_def	sser_addr;
#define		sser		sser_addr.byte

#define		ceie_sser	sser_addr.bit.b0		/* Conflict error interrupt enable bit */
#define		re_sser		sser_addr.bit.b3		/* Receive enable bit */
#define		te_sser		sser_addr.bit.b4		/* Transmit enable bit */
#define		rie_sser	sser_addr.bit.b5		/* Receive interrupt enable bit */
#define		teie_sser	sser_addr.bit.b6		/* Transmit end interrupt enable bit */
#define		tie_sser	sser_addr.bit.b7		/* Transmit interrupt enable bit */

/*------------------------------------------------------
  SS status register
------------------------------------------------------*/
union	byte_def	sssr_addr;
#define		sssr		sssr_addr.byte

#define		ce_sssr		sssr_addr.bit.b0		/* Conflict error flag */
#define		orer_sssr	sssr_addr.bit.b2		/* Overrun error flag */
#define		rdrf_sssr	sssr_addr.bit.b5		/* Receive data register full */
#define		tend_sssr	sssr_addr.bit.b6		/* Transmit end */
#define		tdre_sssr	sssr_addr.bit.b7		/* Transmit data empty */

/*------------------------------------------------------
  SS mode register 2
------------------------------------------------------*/
union	byte_def	ssmr2_addr;
#define		ssmr2		ssmr2_addr.byte

#define		ssums_ssmr2	ssmr2_addr.bit.b0		/* Clock synchronous serial I/O with chip select mode select bit */
#define		csos_ssmr2	ssmr2_addr.bit.b1		/* SCS pin open drain output select bit */
#define		soos_ssmr2	ssmr2_addr.bit.b2		/* SSO pin open drain output select bit */
#define		sckos_ssmr2	ssmr2_addr.bit.b3		/* SSCK pin open drain output select bit */
#define		css0_ssmr2	ssmr2_addr.bit.b4		/* SCS pin selsct bit */
#define		css1_ssmr2	ssmr2_addr.bit.b5		/* SCS pin select bit */
#define		scks_ssmr2	ssmr2_addr.bit.b6		/* SSCK pin select bit */
#define		bide_ssmr2	ssmr2_addr.bit.b7		/* Bidirectional mode enable bit */

/*------------------------------------------------------
  SS transmit data register
------------------------------------------------------*/
union	byte_def	sstdr_addr;
#define		sstdr		sstdr_addr.byte

/*------------------------------------------------------
  SS receive data register
------------------------------------------------------*/
union	byte_def	ssrdr_addr;
#define		ssrdr		ssrdr_addr.byte

/*------------------------------------------------------
  IIC bus control register 1
------------------------------------------------------*/
union	byte_def	iccr1_addr;
#define		iccr1		iccr1_addr.byte

#define		cks0_iccr1	iccr1_addr.bit.b0		/* Transmit clock select bit 3 to 0 */
#define		cks1_iccr1	iccr1_addr.bit.b1		/* Transmit clock select bit 3 to 0 */