s3c44b0x.h

An complete pmp solution for mattel juicebox player. Using crossworks for arm.

#define tcmpb1 ((u32 volatile* const) 0x01d5001c) /* TCMPB1 (Timer Compare Buffer 1) */
#define tcnto1 ((u32 volatile* const) 0x01d50020) /* TCNTO1 (Timer Count Observation 1) */
#define tcntb2 ((u32 volatile* const) 0x01d50024) /* TCNTB2 (Timer Count Buffer 2) */
#define tcmpb2 ((u32 volatile* const) 0x01d50028) /* TCMPB2 (Timer Compare Buffer 2) */
#define tcnto2 ((u32 volatile* const) 0x01d5002c) /* TCNTO2 (Timer Count Observation 2) */
#define tcntb3 ((u32 volatile* const) 0x01d50030) /* TCNTB3 (Timer Count Buffer 3) */
#define tcmpb3 ((u32 volatile* const) 0x01d50034) /* TCMPB3 (Timer Compare Buffer 3) */
#define tcnto3 ((u32 volatile* const) 0x01d50038) /* TCNTO3 (Timer Count Observation 3) */
#define tcntb4 ((u32 volatile* const) 0x01d5003c) /* TCNTB4 (Timer Count Buffer 4) */
#define tcmpb4 ((u32 volatile* const) 0x01d50040) /* TCMPB4 (Timer Compare Buffer 4) */
#define tcnto4 ((u32 volatile* const) 0x01d50044) /* TCNTO4 (Timer Count Observation 4) */
#define tcntb5 ((u32 volatile* const) 0x01d50048) /* TCNTB5 (Timer Count Buffer 5) */
#define tcnto5 ((u32 volatile* const) 0x01d5004c) /* TCNTO5 (Timer Count Observation 5) */

/****** IIC */
#define iiccon ((u32 volatile* const) 0x01d60000) /* IICCON (IIC Control) */
#define iicstat ((u32 volatile* const) 0x01d60004) /* IICSTAT (IIC Status) */
#define iicadd ((u32 volatile* const) 0x01d60008) /* IICADD (IIC Address) */
#define iicds ((u32 volatile* const) 0x01d6000c) /* IICDS (IIC Data Shift) */

/****** RTC */
/* The book shows these as 8 bit registers, not 32.  Double-check? */
#define rtccon ((u32 volatile* const) 0x01d70040) /* RTCCON (RTC Control) */
#define rtcalm ((u32 volatile* const) 0x01d70050) /* RTCALM (RTC Alarm) */
#define almsec ((u32 volatile* const) 0x01d70054) /* ALMSEC (Alarm Second) */
#define almmin ((u32 volatile* const) 0x01d70058) /* ALMMIN (Alarm Minute) */
#define almhour ((u32 volatile* const) 0x01d7005c) /* ALMHOUR (Alarm Hour) */
#define almday ((u32 volatile* const) 0x01d70060) /* ALMDAY (Alarm Day) */
#define almmon ((u32 volatile* const) 0x01d70064) /* ALMMON (Alarm Month) */
#define almyear ((u32 volatile* const) 0x01d70068) /* ALMYEAR (Alarm Year) */
#define rtcrst ((u32 volatile* const) 0x01d7006c) /* RTCRST (RTC Round Reset) */
#define bcdsec ((u32 volatile* const) 0x01d70070) /* BCDSEC (BCD Second) */
#define bcdmin ((u32 volatile* const) 0x01d70074) /* BCDMIN (BCD Minute) */
#define bcdhour ((u32 volatile* const) 0x01d70078) /* BCDHOUR (BCD Hour) */
#define bcdday ((u32 volatile* const) 0x01d7007c) /* BCDDAY (BCD Day) */
#define bcddate ((u32 volatile* const) 0x01d70080) /* BCDDATE (BCD Date) */
#define bcdmon ((u32 volatile* const) 0x01d70084) /* BCDMON (BCD Month) */
#define bcdyear ((u32 volatile* const) 0x01d70088) /* BCDYEAR (BCD Year) */
#define ticint ((u32 volatile* const) 0x01D7008C) /* TICINT (Tick time count) */

/****** CLOCK & POWER MANAGEMENT */
#define pllcon ((u32 volatile* const) 0x01d80000) /* PLLCON (PLL Control) */
#define clkcon ((u32 volatile* const) 0x01d80004) /* CLKCON (Clock Control) */
#define clkslow ((u32 volatile* const) 0x01d80008) /* CLKSLOW (Slow clock Control) */
#define locktime ((u32 volatile* const) 0x01d8000c) /* LOCKTIME (PLL lock time Counter) */

/****** INTERRUPT CONTROLLER */
#define intcon ((u32 volatile* const) 0x01e00000) /* INTCON (Interrupt Control) */
#define intpnd ((u32 volatile* const) 0x01e00004) /* INTPND (Interrupt Request Status) */
#define intmod ((u32 volatile* const) 0x01e00008) /* INTMOD (Interrupt Mode Control) */
#define intmsk ((u32 volatile* const) 0x01e0000c) /* INTMSK (Interrupt Mask Control) */
#define i_pslv ((u32 volatile* const) 0x01e00010) /* I_PSLV (IRQ Interrupt Previous Slave) */
#define i_pmst ((u32 volatile* const) 0x01e00014) /* I_PMST (IRQ Interrupt Priority Master) */
#define i_cslv ((u32 volatile* const) 0x01e00018) /* I_CSLV (IRQ Interrupt Current Slave) */
#define i_cmst ((u32 volatile* const) 0x01e0001c) /* I_CMST (IRQ Interrupt Current Master) */
#define i_ispr ((u32 volatile* const) 0x01e00020) /* I_ISPR (IRQ Interrupt Pending Status) */
#define i_ispc ((u32 volatile* const) 0x01e00024) /* I_ISPC (IRQ Interrupt Pending Clear) */
#define f_ispr ((u32 volatile* const) 0x01e00038) /* F_ISPR (FIQ Interrupt Pending) */
#define f_ispc ((u32 volatile* const) 0x01e0003c) /* F_ISPC (FIQ Interrupt Pending Clear) */

/****** LCD CONTROLLER */
#define lcdcon1 ((u32 volatile* const) 0x01f00000) /* LCDCON1 (LCD Control 1) */
#define lcdcon2 ((u32 volatile* const) 0x01f00004) /* LCDCON2 (LCD Control 2) */
#define lcdcon3 ((u32 volatile* const) 0x01f00040) /* LCDCON3 (LCD Control 3) */
#define lcdsaddr1 ((u32 volatile* const) 0x01f00008) /* LCDSADDR1 (Frame Upper Buffer Start Address 1) */
#define lcdsaddr2 ((u32 volatile* const) 0x01f0000c) /* LCDSADDR2 (Frame Lower Buffer Start Address 2) */
#define lcdsaddr3 ((u32 volatile* const) 0x01f00010) /* LCDSADDR3 (Virtual Screen Address) */
#define redlut ((u32 volatile* const) 0x01f00014) /* REDLUT (RED Lookup Table) */
#define greenlut ((u32 volatile* const) 0x01f00018) /* GREENLUT (GREEN Lookup Table) */
#define bluelut ((u32 volatile* const) 0x01f0001c) /* BLUELUT (BLUE Lookup Table) */
#define dp1_2 ((u32 volatile* const) 0x01f00020) /* DP1_2 (Dithering Pattern duty 1/2) */
#define dp4_7 ((u32 volatile* const) 0x01f00024) /* DP4_7 (Dithering Pattern duty 4/7) */
#define dp3_5 ((u32 volatile* const) 0x01f00028) /* DP3_5 (Dithering Pattern duty 3/5) */
#define dp2_3 ((u32 volatile* const) 0x01f0002c) /* DP2_3 (Dithering Pattern duty 2/3) */
#define dp5_7 ((u32 volatile* const) 0x01f00030) /* DP5_7 (Dithering Pattern duty 5/7) */
#define dp3_4 ((u32 volatile* const) 0x01f00034) /* DP3_4 (Dithering Pattern duty 3/4) */
#define dp4_5 ((u32 volatile* const) 0x01f00038) /* DP4_5 (Dithering Pattern duty 4/5) */
#define dp6_7 ((u32 volatile* const) 0x01f0003c) /* DP6_7 (Dithering Pattern duty 6/7) */
#define dithmode ((u32 volatile* const) 0x01f00044) /* DITHMODE (Dithering Mode) */

/****** DMA */
#define zdcon0 ((u32 volatile* const) 0x01e80000) /* ZDCON0 (ZDMA0 Control) */
#define zdisrc0 ((u32 volatile* const) 0x01e80004) /* ZDISRC0 (ZDMA 0 Initial Source Address) */
#define zdides0 ((u32 volatile* const) 0x01e80008) /* ZDIDES0 (ZDMA 0 Initial Destination Address) */
#define zdicnt0 ((u32 volatile* const) 0x01e8000c) /* ZDICNT0 (ZDMA 0 Initial Transfer Count) */
#define zdcsrc0 ((u32 volatile* const) 0x01e80010) /* ZDCSRC0 (ZDMA 0 Current Source Address) */
#define zdcdes0 ((u32 volatile* const) 0x01e80014) /* ZDCDES0 (ZDMA 0 Current Destination Address) */
#define zdccnt0 ((u32 volatile* const) 0x01e80018) /* ZDCCNT0 (ZDMA 0 Current Transfer Count) */
#define zdcon1 ((u32 volatile* const) 0x01e80020) /* ZDCON1 (ZDMA 1 Control) */
#define zdisrc1 ((u32 volatile* const) 0x01e80024) /* ZDISRC1 (ZDMA 1 Initial Source Address) */
#define zdides1 ((u32 volatile* const) 0x01e80028) /* ZDIDES1 (ZDMA 1 Initial Destination Address) */
#define zdicnt1 ((u32 volatile* const) 0x01e8002c) /* ZDICNT1 (ZDMA 1 Initial Transfer Count) */
#define zdcsrc1 ((u32 volatile* const) 0x01e80030) /* ZDCSRC1 (ZDMA 1 Current Source Address) */
#define zdcdes1 ((u32 volatile* const) 0x01e80034) /* ZDCDES1 (ZDMA 1 Current Destination Address) */
#define zdccnt1 ((u32 volatile* const) 0x01e80038) /* ZDCCNT1 (ZDMA 1 Current Transfer Count) */
#define bdcon0 ((u32 volatile* const) 0x01f80000) /* BDCON0 (BDMA 0 Control) */
#define bdisrc0 ((u32 volatile* const) 0x01f80004) /* BDISRC0 (BDMA 0 Initial Source Address) */
#define bdides0 ((u32 volatile* const) 0x01f80008) /* BDIDES0 (BDMA 0 Initial Destination Address) */
#define bdicnt0 ((u32 volatile* const) 0x01f8000c) /* BDICNT0 (BDMA 0 Initial Transfer Count) */
#define bdcsrc0 ((u32 volatile* const) 0x01f80010) /* BDCSRC0 (BDMA 0 Current Source Address) */
#define bdcdes0 ((u32 volatile* const) 0x01f80014) /* BDCDES0 (BDMA 0 Current Destination Address) */
#define bdccnt0 ((u32 volatile* const) 0x01f80018) /* BDCCNT0 (BDMA 0 Current Transfer Count) */
#define bdcon1 ((u32 volatile* const) 0x01f80020) /* BDCON1 (BDMA 1 Control) */
#define bdisrc1 ((u32 volatile* const) 0x01f80024) /* BDISRC1 (BDMA 1 Initial Source Address) */
#define bdides1 ((u32 volatile* const) 0x01f80028) /* BDIDES1 (BDMA 1 Initial Destination Address) */
#define bdicnt1 ((u32 volatile* const) 0x01f8002c) /* BDICNT1 (BDMA 1 Initial Transfer Count) */
#define bdcsrc1 ((u32 volatile* const) 0x01f80030) /* BDCSRC1 (BDMA 1 Current Source Address) */
#define bdcdes1 ((u32 volatile* const) 0x01f80034) /* BDCDES1 (BDMA 1 Current Destination Address) */
#define bdccnt1 ((u32 volatile* const) 0x01f80038) /* BDCCNT1 (BDMA 1 Current Transfer Count) */

#endif