s3c44b0x.h

An complete pmp solution for mattel juicebox player. Using crossworks for arm.

#ifndef __S3C44B0X_H
#define __S3C44B0X_H

/* CPU register definitions for the Samsung S3C44B0X
   Assumes little endian mode, with all but the UART TX/RX 
   holding registers as 32 bit words.  The RTC regs are probably
   supposed to be 8 bit, but they seem to work as 32.  
   Read-only registers are not defined as such.
*/


/****** CPU WRAPPER */
#define syscfg ((u32 volatile* const) 0x01c00000) /* SYSCFG (System Configuration) */
#define ncachbe0 ((u32 volatile* const) 0x01c00004) /* NCACHBE0 (Non Cacheable Area 0) */
#define ncachbe1 ((u32 volatile* const) 0x01c00008) /* NCACHBE1 (Non Cacheable Area 1) */
#define sbuscon ((u32 volatile* const) 0x01c40000) /* SBUSCON (System Bus Control) */

/****** MEMORY CONTROLLER */
#define bwscon ((u32 volatile* const) 0x01c80000) /* BWSCON (Bus Width & Wait Status Control) */
#define bankcon0 ((u32 volatile* const) 0x01c80004) /* BANKCON0 (Boot ROM Control) */
#define bankcon1 ((u32 volatile* const) 0x01c80008) /* BANKCON1 (BANK1 Control) */
#define bankcon2 ((u32 volatile* const) 0x01c8000c) /* BANKCON2 (BANK2 Control) */
#define bankcon3 ((u32 volatile* const) 0x01c80010) /* BANKCON3 (BANK3 Control) */
#define bankcon4 ((u32 volatile* const) 0x01c80014) /* BANKCON4 (BANK4 Control) */
#define bankcon5 ((u32 volatile* const) 0x01c80018) /* BANKCON5 (BANK5 Control) */
#define bankcon6 ((u32 volatile* const) 0x01c8001c) /* BANKCON6 (BANK6 Control) */
#define bankcon7 ((u32 volatile* const) 0x01c80020) /* BANKCON7 (BANK7 Control) */
#define refresh ((u32 volatile* const) 0x01c80024) /* REFRESH (DRAM/SDRAM Refresh Control) */
#define banksize ((u32 volatile* const) 0x01c80028) /* BANKSIZE (Flexible Bank Size) */
#define mrsrb6 ((u32 volatile* const) 0x01c8002c) /* MRSRB6 (Mode register set for SDRAM) */
#define mrsrb7 ((u32 volatile* const) 0x01c80030) /* MRSRB7 (Mode register set for SDRAM) */

/****** UART */
#define ulcon0 ((u32 volatile* const) 0x01d00000) /* ULCON0 (UART 0 Line Control) */
#define ulcon1 ((u32 volatile* const) 0x01d04000) /* ULCON1 (UART 1 Line Control) */
#define ucon0 ((u32 volatile* const) 0x01d00004) /* UCON0 (UART 0 Control) */
#define ucon1 ((u32 volatile* const) 0x01d04004) /* UCON1 (UART 1 Control) */
#define ufcon0 ((u32 volatile* const) 0x01d00008) /* UFCON0 (UART 0 FIFO Control) */
#define ufcon1 ((u32 volatile* const) 0x01d04008) /* UFCON1 (UART 1 FIFO Control) */
#define umcon0 ((u32 volatile* const) 0x01d0000c) /* UMCON0 (UART 0 Modem Control) */
#define umcon1 ((u32 volatile* const) 0x01d0400c) /* UMCON1 (UART 1 Modem Control) */
#define utrstat0 ((u32 volatile* const) 0x01d00010) /* UTRSTAT0 (UART 0 Tx/Rx Status) */
#define utrstat1 ((u32 volatile* const) 0x01d04010) /* UTRSTAT1 (UART 1 Tx/Rx Status) */
#define uerstat0 ((u32 volatile* const) 0x01d00014) /* UERSTAT0 (UART 0 Rx Error Status) */
#define uerstat1 ((u32 volatile* const) 0x01d04014) /* UERSTAT1 (UART 1 Rx Error Status) */
#define ufstat0 ((u32 volatile* const) 0x01d00018) /* UFSTAT0 (UART 0 FIFO Status) */
#define ufstat1 ((u32 volatile* const) 0x01d04018) /* UFSTAT1 (UART 1 FIFO Status) */
#define umstat0 ((u32 volatile* const) 0x01d0001c) /* UMSTAT0 (UART 0 Modem Status) */
#define umstat1 ((u32 volatile* const) 0x01d0401c) /* UMSTAT1 (UART 1 Modem Status) */
#define utxh0 ((u08 volatile* const) 0x01d00020) /* UTXH0 (UART 0 Transmission Hold) */
#define utxh1 ((u08 volatile* const) 0x01d04020) /* UTXH1 (UART 1 Transmission Hold) */
#define urxh0 ((u08 volatile* const) 0x01d00024) /* URXH0 (UART 0 Receive Buffer) */
#define urxh1 ((u08 volatile* const) 0x01d04024) /* URXH1 (UART 1 Receive Buffer) */
#define ubrdiv0 ((u32 volatile* const) 0x01d00028) /* UBRDIV0 (UART 0 Baud Rate Divisor) */
#define ubrdiv1 ((u32 volatile* const) 0x01d04028) /* UBRDIV1 (UART 1 Baud Rate Divisor) */

/****** SIO */
#define siocon ((u32 volatile* const) 0x01d14000) /* SIOCON (SIO Control) */
#define siodat ((u32 volatile* const) 0x01d14004) /* SIODAT (SIO Data) */
#define sbrdr ((u32 volatile* const) 0x01d14008) /* SBRDR (SIO Baud Rate Prescaler) */
#define itvcnt ((u32 volatile* const) 0x01d1400c) /* ITVCNT (SIO Interval Counter) */
#define dcntz ((u32 volatile* const) 0x01d14010) /* DCNTZ (SIO DMA Count Zero) */

/****** IIS */
#define iiscon ((u32 volatile* const) 0x01d18000) /* IISCON (IIS Control) */
#define iismod ((u32 volatile* const) 0x01d18004) /* IISMOD (IIS Mode) */
#define iispsr ((u32 volatile* const) 0x01d18008) /* IISPSR (IIS Prescaler) */
#define iisfifcon ((u32 volatile* const) 0x01d1800c) /* IISFIFCON (IIS FIFO Control) */
#define iisfif ((u32 volatile* const) 0x01d18010) /* IISFIF (IIS FIFO Entry) */

/****** I/O PORT */
#define pcona ((u32 volatile* const) 0x01d20000) /* PCONA (Port A Control) */
#define pdata ((u32 volatile* const) 0x01d20004) /* PDATA (Port A Data) */
#define pconb ((u32 volatile* const) 0x01d20008) /* PCONB (Port B Control) */
#define pdatb ((u32 volatile* const) 0x01d2000c) /* PDATB (Port B Data) */
#define pconc ((u32 volatile* const) 0x01d20010) /* PCONC (Port C Control) */
#define pdatc ((u32 volatile* const) 0x01d20014) /* PDATC (Port C Data) */
#define pupc ((u32 volatile* const) 0x01d20018) /* PUPC (Pull-up Control C) */
#define pcond ((u32 volatile* const) 0x01d2001c) /* PCOND (Port D Control) */
#define pdatd ((u32 volatile* const) 0x01d20020) /* PDATD (Port D Data) */
#define pupd ((u32 volatile* const) 0x01d20024) /* PUPD (Pull-up Control D) */
#define pcone ((u32 volatile* const) 0x01d20028) /* PCONE (Port E Control) */
#define pdate ((u32 volatile* const) 0x01d2002c) /* PDATE (Port E Data) */
#define pupe ((u32 volatile* const) 0x01d20030) /* PUPE (Pull-up Control E) */
#define pconf ((u32 volatile* const) 0x01d20034) /* PCONF (Port F Control) */
#define pdatf ((u32 volatile* const) 0x01d20038) /* PDATF (Port F Data) */
#define pupf ((u32 volatile* const) 0x01d2003c) /* PUPF (Pull-up Control F) */
#define pcong ((u32 volatile* const) 0x01d20040) /* PCONG (Port G Control) */
#define pdatg ((u32 volatile* const) 0x01d20044) /* PDATG (Port G Data) */
#define pupg ((u32 volatile* const) 0x01d20048) /* PUPG (Pull-up Control G) */
#define spucr ((u32 volatile* const) 0x01d2004c) /* SPUCR (Special Pull-up) */
#define extint ((u32 volatile* const) 0x01d20050) /* EXTINT (External Interrupt Control) */
#define extinpnd ((u32 volatile* const) 0x01d20054) /* EXTINPND (External Interrupt Pending) */

/****** WATCHDOG TIMER */
#define wtcon ((u32 volatile* const) 0x01d30000) /* WTCON (Watchdog Timer Mode) */
#define wtdat ((u32 volatile* const) 0x01d30004) /* WTDAT (Watchdog Timer Data) */
#define wtcnt ((u32 volatile* const) 0x01d30008) /* WTCNT (Watchdog Timer Count) */

/****** A/D CONVERTER */
#define adccon ((u32 volatile* const) 0x01d40000) /* ADCCON (ADC Control) */
#define adcpsr ((u32 volatile* const) 0x01d40004) /* ADCPSR (ADC Prescaler) */
#define adcdat ((u32 volatile* const) 0x01d40008) /* ADCDAT (Digitized 10 bit Data) */

/****** PWM TIMER */
#define tcfg0 ((u32 volatile* const) 0x01d50000) /* TCFG0 (Timer Configuration) */
#define tcfg1 ((u32 volatile* const) 0x01d50004) /* TCFG1 (Timer Configuration) */
#define tcon ((u32 volatile* const) 0x01d50008) /* TCON (Timer Control) */
#define tcntb0 ((u32 volatile* const) 0x01d5000c) /* TCNTB0 (Timer Count Buffer 0) */
#define tcmpb0 ((u32 volatile* const) 0x01d50010) /* TCMPB0 (Timer Compare Buffer 0) */
#define tcnto0 ((u32 volatile* const) 0x01d50014) /* TCNTO0 (Timer Count Observation 0) */
#define tcntb1 ((u32 volatile* const) 0x01d50018) /* TCNTB1 (Timer Count Buffer 1) */