mgaregs.h

Mesa is an open-source implementation of the OpenGL specification - a system for rendering interacti

#define MGAREG_SPECGSTART 			0x2c8c
#define MGAREG_SPECGXINC 			0x2c90
#define MGAREG_SPECGYINC 			0x2c94
#define MGAREG_SPECRSTART 			0x2c80
#define MGAREG_SPECRXINC 			0x2c84
#define MGAREG_SPECRYINC 			0x2c88
#define MGAREG_SRC0 				0x1c30
#define MGAREG_SRC1 				0x1c34
#define MGAREG_SRC2 				0x1c38
#define MGAREG_SRC3 				0x1c3c
#define MGAREG_SRCORG 				0x2cb4

#    define SO_srcmap_MASK 		0xfffffffe 	/* bit 0 */
#    define SO_srcmap_fb 		0x0 		
#    define SO_srcmap_sys 		0x1 		
#    define SO_srcacc_MASK 		0xfffffffd 	/* bit 1 */
#    define SO_srcacc_pci 		0x0 		
#    define SO_srcacc_agp 		0x2 		
#    define SO_srcorg_MASK 		0x7 		/* bits 3-31 */
#    define SO_srcorg_SHIFT 		3 		

#define MGAREG_STATUS 				0x1e14

#    define STAT_softrapen_MASK 	0xfffffffe 	/* bit 0 */
#    define STAT_softrapen_disable 	0x0 		
#    define STAT_softrapen_enable 	0x1 		
#    define STAT_pickpen_MASK 		0xfffffffb 	/* bit 2 */
#    define STAT_pickpen_disable 	0x0 		
#    define STAT_pickpen_enable 	0x4 		
#    define STAT_vsyncsts_MASK 		0xfffffff7 	/* bit 3 */
#    define STAT_vsyncsts_disable 	0x0 		
#    define STAT_vsyncsts_enable 	0x8 		
#    define STAT_vsyncpen_MASK 		0xffffffef 	/* bit 4 */
#    define STAT_vsyncpen_disable 	0x0 		
#    define STAT_vsyncpen_enable 	0x10 		
#    define STAT_vlinepen_MASK 		0xffffffdf 	/* bit 5 */
#    define STAT_vlinepen_disable 	0x0 		
#    define STAT_vlinepen_enable 	0x20 		
#    define STAT_extpen_MASK 		0xffffffbf 	/* bit 6 */
#    define STAT_extpen_disable 	0x0 		
#    define STAT_extpen_enable 		0x40 		
#    define STAT_wpen_MASK 		0xffffff7f 	/* bit 7 */
#    define STAT_wpen_disable 		0x0 		
#    define STAT_wpen_enable 		0x80 		
#    define STAT_wcpen_MASK 		0xfffffeff 	/* bit 8 */
#    define STAT_wcpen_disable 		0x0 		
#    define STAT_wcpen_enable 		0x100 		
#    define STAT_dwgengsts_MASK 	0xfffeffff 	/* bit 16 */
#    define STAT_dwgengsts_disable 	0x0 		
#    define STAT_dwgengsts_enable 	0x10000 	
#    define STAT_endprdmasts_MASK 	0xfffdffff 	/* bit 17 */
#    define STAT_endprdmasts_disable 	0x0 		
#    define STAT_endprdmasts_enable 	0x20000 	
#    define STAT_wbusy_MASK 		0xfffbffff 	/* bit 18 */
#    define STAT_wbusy_disable 		0x0 		
#    define STAT_wbusy_enable 		0x40000 	
#    define STAT_swflag_MASK 		0xfffffff 	/* bits 28-31 */
#    define STAT_swflag_SHIFT 		28 		

#define MGAREG_STENCIL 			0x2cc8

#    define S_sref_MASK 		0xffffff00 	/* bits 0-7 */
#    define S_sref_SHIFT 		0 		
#    define S_smsk_MASK 		0xffff00ff 	/* bits 8-15 */
#    define S_smsk_SHIFT 		8 		
#    define S_swtmsk_MASK 		0xff00ffff 	/* bits 16-23 */
#    define S_swtmsk_SHIFT 		16 		

#define MGAREG_STENCILCTL 			0x2ccc

#    define SC_smode_MASK 		0xfffffff8 	/* bits 0-2 */
#    define SC_smode_salways 		0x0 		/* val 0, shift 0 */
#    define SC_smode_snever 		0x1 		/* val 1, shift 0 */
#    define SC_smode_se 		0x2 		/* val 2, shift 0 */
#    define SC_smode_sne 		0x3 		/* val 3, shift 0 */
#    define SC_smode_slt 		0x4 		/* val 4, shift 0 */
#    define SC_smode_slte 		0x5 		/* val 5, shift 0 */
#    define SC_smode_sgt 		0x6 		/* val 6, shift 0 */
#    define SC_smode_sgte 		0x7 		/* val 7, shift 0 */
#    define SC_sfailop_MASK 		0xffffffc7 	/* bits 3-5 */
#    define SC_sfailop_keep 		0x0 		/* val 0, shift 3 */
#    define SC_sfailop_zero 		0x8 		/* val 1, shift 3 */
#    define SC_sfailop_replace 		0x10 		/* val 2, shift 3 */
#    define SC_sfailop_incrsat 		0x18 		/* val 3, shift 3 */
#    define SC_sfailop_decrsat 		0x20 		/* val 4, shift 3 */
#    define SC_sfailop_invert 		0x28 		/* val 5, shift 3 */
#    define SC_sfailop_incr 		0x30 		/* val 6, shift 3 */
#    define SC_sfailop_decr 		0x38 		/* val 7, shift 3 */
#    define SC_szfailop_MASK 		0xfffffe3f 	/* bits 6-8 */
#    define SC_szfailop_keep 		0x0 		/* val 0, shift 6 */
#    define SC_szfailop_zero 		0x40 		/* val 1, shift 6 */
#    define SC_szfailop_replace 	0x80 		/* val 2, shift 6 */
#    define SC_szfailop_incrsat 	0xc0 		/* val 3, shift 6 */
#    define SC_szfailop_decrsat 	0x100 		/* val 4, shift 6 */
#    define SC_szfailop_invert 		0x140 		/* val 5, shift 6 */
#    define SC_szfailop_incr 		0x180 		/* val 6, shift 6 */
#    define SC_szfailop_decr 		0x1c0 		/* val 7, shift 6 */
#    define SC_szpassop_MASK 		0xfffff1ff 	/* bits 9-11 */
#    define SC_szpassop_keep 		0x0 		/* val 0, shift 9 */
#    define SC_szpassop_zero 		0x200 		/* val 1, shift 9 */
#    define SC_szpassop_replace 	0x400 		/* val 2, shift 9 */
#    define SC_szpassop_incrsat 	0x600 		/* val 3, shift 9 */
#    define SC_szpassop_decrsat 	0x800 		/* val 4, shift 9 */
#    define SC_szpassop_invert 		0xa00 		/* val 5, shift 9 */
#    define SC_szpassop_incr 		0xc00 		/* val 6, shift 9 */
#    define SC_szpassop_decr 		0xe00 		/* val 7, shift 9 */

#define MGAREG_TDUALSTAGE0 			0x2cf8

#    define TD0_color_arg2_MASK 	0xfffffffc 	/* bits 0-1 */
#    define TD0_color_arg2_diffuse 	0x0 		/* val 0, shift 0 */
#    define TD0_color_arg2_specular 	0x1 		/* val 1, shift 0 */
#    define TD0_color_arg2_fcol 	0x2 		/* val 2, shift 0 */
#    define TD0_color_arg2_prevstage 	0x3 		/* val 3, shift 0 */
#    define TD0_color_alpha_MASK 	0xffffffe3 	/* bits 2-4 */
#    define TD0_color_alpha_diffuse 	0x0 		/* val 0, shift 2 */
#    define TD0_color_alpha_fcol 	0x4 		/* val 1, shift 2 */
#    define TD0_color_alpha_currtex 	0x8 		/* val 2, shift 2 */
#    define TD0_color_alpha_prevtex 	0xc 		/* val 3, shift 2 */
#    define TD0_color_alpha_prevstage 	0x10 		/* val 4, shift 2 */
#    define TD0_color_arg1_replicatealpha_MASK 0xffffffdf 	/* bit 5 */
#    define TD0_color_arg1_replicatealpha_disable 0x0 		
#    define TD0_color_arg1_replicatealpha_enable 0x20 		
#    define TD0_color_arg1_inv_MASK 	0xffffffbf 	/* bit 6 */
#    define TD0_color_arg1_inv_disable 	0x0 		
#    define TD0_color_arg1_inv_enable 	0x40 		
#    define TD0_color_arg2_replicatealpha_MASK 0xffffff7f 	/* bit 7 */
#    define TD0_color_arg2_replicatealpha_disable 0x0 		
#    define TD0_color_arg2_replicatealpha_enable 0x80 		
#    define TD0_color_arg2_inv_MASK 	0xfffffeff 	/* bit 8 */
#    define TD0_color_arg2_inv_disable 	0x0 		
#    define TD0_color_arg2_inv_enable 	0x100 		
#    define TD0_color_alpha1inv_MASK 	0xfffffdff 	/* bit 9 */
#    define TD0_color_alpha1inv_disable 0x0 		
#    define TD0_color_alpha1inv_enable 	0x200 		
#    define TD0_color_alpha2inv_MASK 	0xfffffbff 	/* bit 10 */
#    define TD0_color_alpha2inv_disable 0x0 		
#    define TD0_color_alpha2inv_enable 	0x400 		
#    define TD0_color_arg1mul_MASK 	0xfffff7ff 	/* bit 11 */
#    define TD0_color_arg1mul_disable 	0x0 		/* val 0, shift 11 */
#    define TD0_color_arg1mul_alpha1 	0x800 		/* val 1, shift 11 */
#    define TD0_color_arg2mul_MASK 	0xffffefff 	/* bit 12 */
#    define TD0_color_arg2mul_disable 	0x0 		/* val 0, shift 12 */
#    define TD0_color_arg2mul_alpha2 	0x1000 		/* val 1, shift 12 */
#    define TD0_color_arg1add_MASK 	0xffffdfff 	/* bit 13 */
#    define TD0_color_arg1add_disable 	0x0 		/* val 0, shift 13 */
#    define TD0_color_arg1add_mulout 	0x2000 		/* val 1, shift 13 */
#    define TD0_color_arg2add_MASK 	0xffffbfff 	/* bit 14 */
#    define TD0_color_arg2add_disable 	0x0 		/* val 0, shift 14 */
#    define TD0_color_arg2add_mulout 	0x4000 		/* val 1, shift 14 */
#    define TD0_color_modbright_MASK 	0xfffe7fff 	/* bits 15-16 */
#    define TD0_color_modbright_disable 0x0 		/* val 0, shift 15 */
#    define TD0_color_modbright_2x 	0x8000 		/* val 1, shift 15 */
#    define TD0_color_modbright_4x 	0x10000 	/* val 2, shift 15 */
#    define TD0_color_add_MASK 		0xfffdffff 	/* bit 17 */
#    define TD0_color_add_sub 		0x0 		/* val 0, shift 17 */
#    define TD0_color_add_add 		0x20000 	/* val 1, shift 17 */
#    define TD0_color_add2x_MASK 	0xfffbffff 	/* bit 18 */
#    define TD0_color_add2x_disable 	0x0 		
#    define TD0_color_add2x_enable 	0x40000 	
#    define TD0_color_addbias_MASK 	0xfff7ffff 	/* bit 19 */
#    define TD0_color_addbias_disable 	0x0 		
#    define TD0_color_addbias_enable 	0x80000 	
#    define TD0_color_blend_MASK 	0xffefffff 	/* bit 20 */
#    define TD0_color_blend_disable 	0x0 		
#    define TD0_color_blend_enable 	0x100000 	
#    define TD0_color_sel_MASK 		0xff9fffff 	/* bits 21-22 */
#    define TD0_color_sel_arg1 		0x0 		/* val 0, shift 21 */
#    define TD0_color_sel_arg2 		0x200000 	/* val 1, shift 21 */
#    define TD0_color_sel_add 		0x400000 	/* val 2, shift 21 */
#    define TD0_color_sel_mul 		0x600000 	/* val 3, shift 21 */
#    define TD0_alpha_arg1_inv_MASK 	0xff7fffff 	/* bit 23 */
#    define TD0_alpha_arg1_inv_disable 	0x0 		
#    define TD0_alpha_arg1_inv_enable 	0x800000 	
#    define TD0_alpha_arg2_MASK 	0xfcffffff 	/* bits 24-25 */
#    define TD0_alpha_arg2_diffuse 	0x0 		/* val 0, shift 24 */
#    define TD0_alpha_arg2_fcol 	0x1000000 	/* val 1, shift 24 */
#    define TD0_alpha_arg2_prevtex 	0x2000000 	/* val 2, shift 24 */
#    define TD0_alpha_arg2_prevstage 	0x3000000 	/* val 3, shift 24 */
#    define TD0_alpha_arg2_inv_MASK 	0xfbffffff 	/* bit 26 */
#    define TD0_alpha_arg2_inv_disable 	0x0 		
#    define TD0_alpha_arg2_inv_enable 	0x4000000 	
#    define TD0_alpha_add_MASK 		0xf7ffffff 	/* bit 27 */
#    define TD0_alpha_add_disable 	0x0 		
#    define TD0_alpha_add_enable 	0x8000000 	
#    define TD0_alpha_addbias_MASK 	0xefffffff 	/* bit 28 */
#    define TD0_alpha_addbias_disable 	0x0 		
#    define TD0_alpha_addbias_enable 	0x10000000 	
#    define TD0_alpha_add2x_MASK 	0xdfffffff 	/* bit 29 */
#    define TD0_alpha_add2x_disable 	0x0 		
#    define TD0_alpha_add2x_enable 	0x20000000 	
#    define TD0_alpha_modbright_MASK 	0xcfffffff 	/* bits 28-29 */
#    define TD0_alpha_modbright_disable 0x0 		/* val 0, shift 28 */
#    define TD0_alpha_modbright_2x 	0x10000000 	/* val 1, shift 28 */
#    define TD0_alpha_modbright_4x 	0x20000000 	/* val 2, shift 28 */
#    define TD0_alpha_sel_MASK 		0x3fffffff 	/* bits 30-31 */
#    define TD0_alpha_sel_arg1 		0x0 		/* val 0, shift 30 */
#    define TD0_alpha_sel_arg2 		0x40000000 	/* val 1, shift 30 */
#    define TD0_alpha_sel_add 		0x80000000 	/* val 2, shift 30 */
#    define TD0_alpha_sel_mul 		0xc0000000 	/* val 3, shift 30 */

#define MGAREG_TDUALSTAGE1 			0x2cfc

#    define TD1_color_arg2_MASK 	0xfffffffc 	/* bits 0-1 */
#    define TD1_color_arg2_diffuse 	0x0 		/* val 0, shift 0 */
#    define TD1_color_arg2_specular 	0x1 		/* val 1, shift 0 */
#    define TD1_color_arg2_fcol 	0x2 		/* val 2, shift 0 */
#    define TD1_color_arg2_prevstage 	0x3 		/* val 3, shift 0 */
#    define TD1_color_alpha_MASK 	0xffffffe3 	/* bits 2-4 */
#    define TD1_color_alpha_diffuse 	0x0 		/* val 0, shift 2 */
#    define TD1_color_alpha_fcol 	0x4 		/* val 1, shift 2 */
#    define TD1_color_alpha_tex0 	0x8 		/* val 2, shift 2 */
#    define TD1_color_alpha_prevtex 	0xc 		/* val 3, shift 2 */
#    define TD1_color_alpha_prevstage 	0x10 		/* val 4, shift 2 */
#    define TD1_color_arg1_replicatealpha_MASK 0xffffffdf 	/* bit 5 */
#    define TD1_color_arg1_replicatealpha_disable 0x0 		
#    define TD1_color_arg1_replicatealpha_enable 0x20 		
#    define TD1_color_arg1_inv_MASK 	0xffffffbf 	/* bit 6 */
#    define TD1_color_arg1_inv_disable 	0x0 		
#    define TD1_color_arg1_inv_enable 	0x40 		
#    define TD1_color_arg2_replicatealpha_MASK 0xffffff7f 	/* bit 7 */
#    define TD1_color_arg2_replicatealpha_disable 0x0 		
#    define TD1_color_arg2_replicatealpha_enable 0x80 		
#    define TD1_color_arg2_inv_MASK 	0xfffffeff 	/* bit 8 */
#    define TD1_color_arg2_inv_disable 	0x0 		
#    define TD1_color_arg2_inv_enable 	0x100 		
#    define TD1_color_alpha1inv_MASK 	0xfffffdff 	/* bit 9 */
#    define TD1_color_alpha1inv_disable 0x0 		
#    define TD1_color_alpha1inv_enable 	0x200 		
#    define TD1_color_alpha2inv_MASK 	0xfffffbff 	/* bit 10 */
#    define TD1_color_alpha2inv_disable 0x0 		
#    define TD1_color_alpha2inv_enable 	0x400 		
#    define TD1_color_arg1mul_MASK 	0xfffff7ff 	/* bit 11 */
#    define TD1_color_arg1mul_disable 	0x0 		/* val 0, shift 11 */
#    define TD1_color_arg1mul_alpha1 	0x800 		/* val 1, shift 11 */
#    define TD1_color_arg2mul_MASK 	0xffffefff 	/* bit 12 */
#    define TD1_color_arg2mul_disable 	0x0 		/* val 0, shift 12 */
#    define TD1_color_arg2mul_alpha2 	0x1000 		/* val 1, shift 12 */
#    define TD1_color_arg1add_MASK 	0xffffdfff 	/* bit 13 */
#    define TD1_color_arg1add_disable 	0x0 		/* val 0, shift 13 */
#    define TD1_color_arg1add_mulout 	0x2000 		/* val 1, shift 13 */
#    define TD1_color_arg2add_MASK 	0xffffbfff 	/* bit 14 */
#    define TD1_color_arg2add_disable 	0x0 		/* val 0, shift 14 */
#    define TD1_color_arg2add_mulout 	0x4000 		/* val 1, shift 14 */
#    define TD1_color_modbright_MASK 	0xfffe7fff 	/* bits 15-16 */
#    define TD1_color_modbright_disable 0x0 		/* val 0, shift 15 */
#    define TD1_color_modbright_2x 	0x8000 		/* val 1, shift 15 */
#    define TD1_color_modbright_4x 	0x10000 	/* val 2, shift 15 */
#    define TD1_color_add_MASK 		0xfffdffff 	/* bit 17 */
#    define TD1_color_add_sub 		0x0 		/* val 0, shift 17 */
#    define TD1_color_add_add 		0x20000 	/* val 1, shift 17 */
#    define TD1_color_add2x_MASK 	0xfffbffff 	/* bit 18 */
#    define TD1_color_add2x_disable 	0x0 		
#    define TD1_color_add2x_enable 	0x40000 	
#    define TD1_color_addbias_MASK 	0xfff7ffff 	/* bit 19 */
#    define TD1_color_addbias_disable 	0x0 		
#    define TD1_color_addbias_enable 	0x80000 	
#    define TD1_color_blend_MASK 	0xffefffff 	/* bit 20 */
#    define TD1_color_blend_disable 	0x0 		
#    define TD1_color_blend_enable 	0x100000 	
#    define TD1_color_sel_MASK 		0xff9fffff 	/* bits 21-22 */
#    define TD1_color_sel_arg1 		0x0 		/* val 0, shift 21 */
#    define TD1_color_sel_arg2 		0x200000 	/* val 1, shift 21 */
#    define TD1_color_sel_add 		0x400000 	/* val 2, shift 21 */
#    define TD1_color_sel_mul 		0x600000 	/* val 3, shift 21 */
#    define TD1_alpha_arg1_inv_MASK 	0xff7fffff 	/* bit 23 */
#    define TD1_alpha_arg1_inv_disable 	0x0 		
#    define TD1_alpha_arg1_inv_enable 	0x800000 	
#    define TD1_alpha_arg2_MASK 	0xfcffffff 	/* bits 24-25 */
#    define TD1_alpha_arg2_diffuse 	0x0 		/* val 0, shift 24 */
#    define TD1_alpha_arg2_fcol 	0x1000000 	/* val 1, shift 24 */
#    define TD1_alpha_arg2_prevtex 	0x2000000 	/* val 2, shift 24 */
#    define TD1_alpha_arg2_prevstage 	0x3000000 	/* val 3, shift 24 */
#    define TD1_alpha_arg2_inv_MASK 	0xfbffffff 	/* bit 26 */
#    define TD1_alpha_arg2_inv_disable 	0x0 		
#    define TD1_alpha_arg2_inv_enable 	0x4000000 	
#    define TD1_alpha_add_MASK 		0xf7ffffff 	/* bit 27 */
#    define TD1_alpha_add_disable 	0x0 		
#    define TD1_alpha_add_enable 	0x8000000 	
#    define TD1_alpha_addbias_MASK 	0xefffffff 	/* bit 28 */
#    define TD1_alpha_addbias_disable 	0x0 		
#    define TD1_alpha_addbias_enable 	0x10000000 	
#    define TD1_alpha_add2x_MASK 	0xdfffffff 	/* bit 29 */
#    define TD1_alpha_add2x_disable 	0x0 		
#    define TD1_alpha_add2x_enable 	0x20000000 	
#    define TD1_alpha_modbright_MASK 	0xcfffffff 	/* bits 28-29 */
#    define TD1_alpha_modbright_disable 0x0 		/* val 0, shift 28 */
#    define TD1_alpha_modbright_2x 	0x10000000 	/* val 1, shift 28 */
#    define TD1_alpha_modbright_4x 	0x20000000 	/* val 2, shift 28 */
#    define TD1_alpha_sel_MASK 		0x3fffffff 	/* bits 30-31 */
#    define TD1_alpha_sel_arg1 		0x0 		/* val 0, shift 30 */
#    define TD1_alpha_sel_arg2 		0x40000000 	/* val 1, shift 30 */
#    define TD1_alpha_sel_add 		0x80000000 	/* val 2, shift 30 */
#    define TD1_alpha_sel_mul 		0xc0000000 	/* val 3, shift 30 */

#define MGAREG_TEST0 				0x1e48

#    define TST_ramtsten_MASK 		0xfffffffe 	/* bit 0 */
#    define TST_ramtsten_disable 	0x0 		
#    define TST_ramtsten_enable 	0x1 		
#    define TST_ramtstdone_MASK 	0xfffffffd 	/* bit 1 */
#    define TST_ramtstdone_disable 	0x0 		
#    define TST_ramtstdone_enable 	0x2 		
#    define TST_wramtstpass_MASK 	0xfffffffb 	/* bit 2 */
#    define TST_wramtstpass_disable 	0x0 		
#    define TST_wramtstpass_enable 	0x4 		
#    define TST_tcachetstpass_MASK 	0xfffffff7 	/* bit 3 */
#    define TST_tcachetstpass_disable 	0x0 		
#    define TST_tcachetstpass_enable 	0x8 		
#    define TST_tluttstpass_MASK 	0xffffffef 	/* bit 4 */
#    define TST_tluttstpass_disable 	0x0 		
#    define TST_tluttstpass_enable 	0x10 		
#    define TST_luttstpass_MASK 	0xffffffdf 	/* bit 5 */
#    define TST_luttstpass_disable 	0x0 		
#    define TST_luttstpass_enable 	0x20 		
#    define TST_besramtstpass_MASK 	0xffffffbf 	/* bit 6 */
#    define TST_besramtstpass_disable 	0x0 		
#    define TST_besramtstpass_enable 	0x40 		
#    define TST_ringen_MASK 		0xfffffeff 	/* bit 8 */
#    define TST_ringen_disable 		0x0 		
#    define TST_ringen_enable 		0x100 		
#    define TST_apllbyp_MASK 		0xfffffdff 	/* bit 9 */
#    define TST_apllbyp_disable 	0x0 		
#    define TST_apllbyp_enable 		0x200 		
#    define TST_hiten_MASK 		0xfffffbff 	/* bit 10 */
#    define TST_hiten_disable 		0x0 		
#    define TST_hiten_enable 		0x400 		
#    define TST_tmode_MASK 		0xffffc7ff 	/* bits 11-13 */
#    define TST_tmode_SHIFT 		11 		
#    define TST_tclksel_MASK 		0xfffe3fff 	/* bits 14-16 */
#    define TST_tclksel_SHIFT 		14 		
#    define TST_ringcnten_MASK 		0xfffdffff 	/* bit 17 */
#    define TST_ringcnten_disable 	0x0 		
#    define TST_ringcnten_enable 	0x20000 	
#    define TST_ringcnt_MASK 		0xc003ffff 	/* bits 18-29 */
#    define TST_ringcnt_SHIFT 		18 		
#    define TST_ringcntclksl_MASK 	0xbfffffff 	/* bit 30 */
#    define TST_ringcntclksl_disable 	0x0 		
#    define TST_ringcntclksl_enable 	0x40000000 	
#    define TST_biosboot_MASK 		0x7fffffff 	/* bit 31 */
#    define TST_biosboot_disable 	0x0 		
#    define TST_biosboot_enable 	0x80000000 	

#define MGAREG_TEXBORDERCOL 			0x2c5c
#define MGAREG_TEXCTL 				0x2c30

#    define TMC_tformat_MASK 		0xfffffff0 	/* bits 0-3 */
#    define TMC_tformat_tw4 		0x0 		/* val 0, shift 0 */
#    define TMC_tformat_tw8 		0x1 		/* val 1, shift 0 */