mgaregs.h

Mesa is an open-source implementation of the OpenGL specification - a system for rendering interacti

/* author: stephen crowley, [e-mail] */

/*
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * STEPHEN CROWLEY, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 
 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
/* $XFree86: xc/lib/GL/mesa/src/drv/mga/mgaregs.h,v 1.6 2003/01/12 03:55:46 tsi Exp $ */

#ifndef _MGAREGS_H_
#define _MGAREGS_H_

/*************** (START) AUTOMATICLY GENERATED REGISTER FILE *****************/
/*
 * Generated on Wed Jan 26 13:44:46 MST 2000
 */



/*
 * Power Graphic Mode Memory Space Registers
 */

#define MGAREG_MGA_EXEC 			0x0100
#define MGAREG_AGP_PLL 			0x1e4c

#    define AGP_PLL_agp2xpllen_MASK 	0xfffffffe 	/* bit 0 */
#    define AGP_PLL_agp2xpllen_disable 	0x0 		
#    define AGP_PLL_agp2xpllen_enable 	0x1 		

#define MGAREG_CFG_OR 				0x1e4c

#    define CFG_OR_comp_or_MASK 	0xfffffff7 	/* bit 3 */
#    define CFG_OR_comp_or_disable 	0x0 		
#    define CFG_OR_comp_or_enable 	0x8 		
#    define CFG_OR_compfreq_MASK 	0xffffff0f 	/* bits 4-7 */
#    define CFG_OR_compfreq_SHIFT 	4 		
#    define CFG_OR_comporup_MASK 	0xfffff0ff 	/* bits 8-11 */
#    define CFG_OR_comporup_SHIFT 	8 		
#    define CFG_OR_compordn_MASK 	0xffff0fff 	/* bits 12-15 */
#    define CFG_OR_compordn_SHIFT 	12 		
#    define CFG_OR_e2pq_MASK 		0xfffeffff 	/* bit 16 */
#    define CFG_OR_e2pq_disable 	0x0 		
#    define CFG_OR_e2pq_enable 		0x10000 	
#    define CFG_OR_e2pqbypcsn_MASK 	0xfffdffff 	/* bit 17 */
#    define CFG_OR_e2pqbypcsn_disable 	0x0 		
#    define CFG_OR_e2pqbypcsn_enable 	0x20000 	
#    define CFG_OR_e2pqbypd_MASK 	0xfffbffff 	/* bit 18 */
#    define CFG_OR_e2pqbypd_disable 	0x0 		
#    define CFG_OR_e2pqbypd_enable 	0x40000 	
#    define CFG_OR_e2pbypclk_MASK 	0xfff7ffff 	/* bit 19 */
#    define CFG_OR_e2pbypclk_disable 	0x0 		
#    define CFG_OR_e2pbypclk_enable 	0x80000 	
#    define CFG_OR_e2pbyp_MASK 		0xffefffff 	/* bit 20 */
#    define CFG_OR_e2pbyp_disable 	0x0 		
#    define CFG_OR_e2pbyp_enable 	0x100000 	
#    define CFG_OR_rate_cap_or_MASK 	0xff1fffff 	/* bits 21-23 */
#    define CFG_OR_rate_cap_or_SHIFT 	21 		
#    define CFG_OR_rq_or_MASK 		0xe0ffffff 	/* bits 24-28 */
#    define CFG_OR_rq_or_SHIFT 		24 		

#define MGAREG_ALPHACTRL 			0x2c7c

#    define AC_src_MASK 		0xfffffff0 	/* bits 0-3 */
#    define AC_src_zero 		0x0 		/* val 0, shift 0 */
#    define AC_src_one 			0x1 		/* val 1, shift 0 */
#    define AC_src_dst_color 		0x2 		/* val 2, shift 0 */
#    define AC_src_om_dst_color 	0x3 		/* val 3, shift 0 */
#    define AC_src_src_alpha 		0x4 		/* val 4, shift 0 */
#    define AC_src_om_src_alpha 	0x5 		/* val 5, shift 0 */
#    define AC_src_dst_alpha 		0x6 		/* val 6, shift 0 */
#    define AC_src_om_dst_alpha 	0x7 		/* val 7, shift 0 */
#    define AC_src_src_alpha_sat 	0x8 		/* val 8, shift 0 */
#    define AC_dst_MASK 		0xffffff0f 	/* bits 4-7 */
#    define AC_dst_zero 		0x0 		/* val 0, shift 4 */
#    define AC_dst_one 			0x10 		/* val 1, shift 4 */
#    define AC_dst_src_color 		0x20 		/* val 2, shift 4 */
#    define AC_dst_om_src_color 	0x30 		/* val 3, shift 4 */
#    define AC_dst_src_alpha 		0x40 		/* val 4, shift 4 */
#    define AC_dst_om_src_alpha 	0x50 		/* val 5, shift 4 */
#    define AC_dst_dst_alpha 		0x60 		/* val 6, shift 4 */
#    define AC_dst_om_dst_alpha 	0x70 		/* val 7, shift 4 */
#    define AC_amode_MASK 		0xfffffcff 	/* bits 8-9 */
#    define AC_amode_FCOL 		0x0 		/* val 0, shift 8 */
#    define AC_amode_alpha_channel 	0x100 		/* val 1, shift 8 */
#    define AC_amode_video_alpha 	0x200 		/* val 2, shift 8 */
#    define AC_amode_RSVD 		0x300 		/* val 3, shift 8 */
#    define AC_astipple_MASK 		0xfffff7ff 	/* bit 11 */
#    define AC_astipple_disable 	0x0 		
#    define AC_astipple_enable 		0x800 		
#    define AC_aten_MASK 		0xffffefff 	/* bit 12 */
#    define AC_aten_disable 		0x0 		
#    define AC_aten_enable 		0x1000 		
#    define AC_atmode_MASK 		0xffff1fff 	/* bits 13-15 */
#    define AC_atmode_noacmp 		0x0 		/* val 0, shift 13 */
#    define AC_atmode_ae 		0x4000 		/* val 2, shift 13 */
#    define AC_atmode_ane 		0x6000 		/* val 3, shift 13 */
#    define AC_atmode_alt 		0x8000 		/* val 4, shift 13 */
#    define AC_atmode_alte 		0xa000 		/* val 5, shift 13 */
#    define AC_atmode_agt 		0xc000 		/* val 6, shift 13 */
#    define AC_atmode_agte 		0xe000 		/* val 7, shift 13 */
#    define AC_atref_MASK 		0xff00ffff 	/* bits 16-23 */
#    define AC_atref_SHIFT 		16 		
#    define AC_alphasel_MASK 		0xfcffffff 	/* bits 24-25 */
#    define AC_alphasel_fromtex 	0x0 		/* val 0, shift 24 */
#    define AC_alphasel_diffused 	0x1000000 	/* val 1, shift 24 */
#    define AC_alphasel_modulated 	0x2000000 	/* val 2, shift 24 */
#    define AC_alphasel_trans 		0x3000000 	/* val 3, shift 24 */

#define MGAREG_ALPHASTART 			0x2c70
#define MGAREG_ALPHAXINC 			0x2c74
#define MGAREG_ALPHAYINC 			0x2c78
#define MGAREG_AR0 				0x1c60

#    define AR0_ar0_MASK 		0xfffc0000 	/* bits 0-17 */
#    define AR0_ar0_SHIFT 		0 		

#define MGAREG_AR1 				0x1c64

#    define AR1_ar1_MASK 		0xff000000 	/* bits 0-23 */
#    define AR1_ar1_SHIFT 		0 		

#define MGAREG_AR2 				0x1c68

#    define AR2_ar2_MASK 		0xfffc0000 	/* bits 0-17 */
#    define AR2_ar2_SHIFT 		0 		

#define MGAREG_AR3 				0x1c6c

#    define AR3_ar3_MASK 		0xff000000 	/* bits 0-23 */
#    define AR3_ar3_SHIFT 		0 		
#    define AR3_spage_MASK 		0xf8ffffff 	/* bits 24-26 */
#    define AR3_spage_SHIFT 		24 		

#define MGAREG_AR4 				0x1c70

#    define AR4_ar4_MASK 		0xfffc0000 	/* bits 0-17 */
#    define AR4_ar4_SHIFT 		0 		

#define MGAREG_AR5 				0x1c74

#    define AR5_ar5_MASK 		0xfffc0000 	/* bits 0-17 */
#    define AR5_ar5_SHIFT 		0 		

#define MGAREG_AR6 				0x1c78

#    define AR6_ar6_MASK 		0xfffc0000 	/* bits 0-17 */
#    define AR6_ar6_SHIFT 		0 		

#define MGAREG_BCOL 				0x1c20
#define MGAREG_BESA1CORG 			0x3d10
#define MGAREG_BESA1ORG 			0x3d00
#define MGAREG_BESA2CORG 			0x3d14
#define MGAREG_BESA2ORG 			0x3d04
#define MGAREG_BESB1CORG 			0x3d18
#define MGAREG_BESB1ORG 			0x3d08
#define MGAREG_BESB2CORG 			0x3d1c
#define MGAREG_BESB2ORG 			0x3d0c
#define MGAREG_BESCTL 				0x3d20

#    define BC_besen_MASK 		0xfffffffe 	/* bit 0 */
#    define BC_besen_disable 		0x0 		
#    define BC_besen_enable 		0x1 		
#    define BC_besv1srcstp_MASK 	0xffffffbf 	/* bit 6 */
#    define BC_besv1srcstp_even 	0x0 		
#    define BC_besv1srcstp_odd 		0x40 		
#    define BC_besv2srcstp_MASK 	0xfffffeff 	/* bit 8 */
#    define BC_besv2srcstp_disable 	0x0 		
#    define BC_besv2srcstp_enable 	0x100 		
#    define BC_beshfen_MASK 		0xfffffbff 	/* bit 10 */
#    define BC_beshfen_disable 		0x0 		
#    define BC_beshfen_enable 		0x400 		
#    define BC_besvfen_MASK 		0xfffff7ff 	/* bit 11 */
#    define BC_besvfen_disable 		0x0 		
#    define BC_besvfen_enable 		0x800 		
#    define BC_beshfixc_MASK 		0xffffefff 	/* bit 12 */
#    define BC_beshfixc_weight 		0x0 		
#    define BC_beshfixc_coeff 		0x1000 		
#    define BC_bescups_MASK 		0xfffeffff 	/* bit 16 */
#    define BC_bescups_disable 		0x0 		
#    define BC_bescups_enable 		0x10000 	
#    define BC_bes420pl_MASK 		0xfffdffff 	/* bit 17 */
#    define BC_bes420pl_422 		0x0 		
#    define BC_bes420pl_420 		0x20000 	
#    define BC_besdith_MASK 		0xfffbffff 	/* bit 18 */
#    define BC_besdith_disable 		0x0 		
#    define BC_besdith_enable 		0x40000 	
#    define BC_beshmir_MASK 		0xfff7ffff 	/* bit 19 */
#    define BC_beshmir_disable 		0x0 		
#    define BC_beshmir_enable 		0x80000 	
#    define BC_besbwen_MASK 		0xffefffff 	/* bit 20 */
#    define BC_besbwen_color 		0x0 		
#    define BC_besbwen_bw 		0x100000 	
#    define BC_besblank_MASK 		0xffdfffff 	/* bit 21 */
#    define BC_besblank_disable 	0x0 		
#    define BC_besblank_enable 		0x200000 	
#    define BC_besfselm_MASK 		0xfeffffff 	/* bit 24 */
#    define BC_besfselm_soft 		0x0 		
#    define BC_besfselm_hard 		0x1000000 	
#    define BC_besfsel_MASK 		0xf9ffffff 	/* bits 25-26 */
#    define BC_besfsel_a1 		0x0 		/* val 0, shift 25 */
#    define BC_besfsel_a2 		0x2000000 	/* val 1, shift 25 */
#    define BC_besfsel_b1 		0x4000000 	/* val 2, shift 25 */
#    define BC_besfsel_b2 		0x6000000 	/* val 3, shift 25 */

#define MGAREG_BESGLOBCTL 			0x3dc0

#    define BGC_beshzoom_MASK 		0xfffffffe 	/* bit 0 */
#    define BGC_beshzoom_disable 	0x0 		
#    define BGC_beshzoom_enable 	0x1 		
#    define BGC_beshzoomf_MASK 		0xfffffffd 	/* bit 1 */
#    define BGC_beshzoomf_disable 	0x0 		
#    define BGC_beshzoomf_enable 	0x2 		
#    define BGC_bescorder_MASK 		0xfffffff7 	/* bit 3 */
#    define BGC_bescorder_even 		0x0 		
#    define BGC_bescorder_odd 		0x8 		
#    define BGC_besreghup_MASK 		0xffffffef 	/* bit 4 */
#    define BGC_besreghup_disable 	0x0 		
#    define BGC_besreghup_enable 	0x10 		
#    define BGC_besvcnt_MASK 		0xf000ffff 	/* bits 16-27 */
#    define BGC_besvcnt_SHIFT 		16 		

#define MGAREG_BESHCOORD 			0x3d28

#    define BHC_besright_MASK 		0xfffff800 	/* bits 0-10 */
#    define BHC_besright_SHIFT 		0 		
#    define BHC_besleft_MASK 		0xf800ffff 	/* bits 16-26 */
#    define BHC_besleft_SHIFT 		16 		

#define MGAREG_BESHISCAL 			0x3d30

#    define BHISF_beshiscal_MASK 	0xffe00003 	/* bits 2-20 */
#    define BHISF_beshiscal_SHIFT 	2 		

#define MGAREG_BESHSRCEND 			0x3d3c

#    define BHSE_beshsrcend_MASK 	0xfc000003 	/* bits 2-25 */
#    define BHSE_beshsrcend_SHIFT 	2 		

#define MGAREG_BESHSRCLST 			0x3d50

#    define BHSL_beshsrclst_MASK 	0xfc00ffff 	/* bits 16-25 */
#    define BHSL_beshsrclst_SHIFT 	16 		

#define MGAREG_BESHSRCST 			0x3d38

#    define BHSS_beshsrcst_MASK 	0xfc000003 	/* bits 2-25 */
#    define BHSS_beshsrcst_SHIFT 	2 		

#define MGAREG_BESPITCH 			0x3d24

#    define BP_bespitch_MASK 		0xfffff000 	/* bits 0-11 */
#    define BP_bespitch_SHIFT 		0 		

#define MGAREG_BESSTATUS 			0x3dc4

#    define BS_besstat_MASK 		0xfffffffc 	/* bits 0-1 */
#    define BS_besstat_a1 		0x0 		/* val 0, shift 0 */
#    define BS_besstat_a2 		0x1 		/* val 1, shift 0 */
#    define BS_besstat_b1 		0x2 		/* val 2, shift 0 */
#    define BS_besstat_b2 		0x3 		/* val 3, shift 0 */

#define MGAREG_BESV1SRCLST 			0x3d54

#    define BSF_besv1srclast_MASK 	0xfffffc00 	/* bits 0-9 */
#    define BSF_besv1srclast_SHIFT 	0 		

#define MGAREG_BESV2SRCLST 			0x3d58

#    define BSF_besv2srclst_MASK 	0xfffffc00 	/* bits 0-9 */
#    define BSF_besv2srclst_SHIFT 	0 		

#define MGAREG_BESV1WGHT 			0x3d48

#    define BSF_besv1wght_MASK 		0xffff0003 	/* bits 2-15 */
#    define BSF_besv1wght_SHIFT 	2 		
#    define BSF_besv1wghts_MASK 	0xfffeffff 	/* bit 16 */
#    define BSF_besv1wghts_disable 	0x0 		
#    define BSF_besv1wghts_enable 	0x10000 	

#define MGAREG_BESV2WGHT 			0x3d4c

#    define BSF_besv2wght_MASK 		0xffff0003 	/* bits 2-15 */
#    define BSF_besv2wght_SHIFT 	2 		
#    define BSF_besv2wghts_MASK 	0xfffeffff 	/* bit 16 */
#    define BSF_besv2wghts_disable 	0x0 		
#    define BSF_besv2wghts_enable 	0x10000 	

#define MGAREG_BESVCOORD 			0x3d2c

#    define BVC_besbot_MASK 		0xfffff800 	/* bits 0-10 */
#    define BVC_besbot_SHIFT 		0 		
#    define BVC_bestop_MASK 		0xf800ffff 	/* bits 16-26 */
#    define BVC_bestop_SHIFT 		16 		

#define MGAREG_BESVISCAL 			0x3d34

#    define BVISF_besviscal_MASK 	0xffe00003 	/* bits 2-20 */
#    define BVISF_besviscal_SHIFT 	2 		

#define MGAREG_CODECADDR 			0x3e44
#define MGAREG_CODECCTL 			0x3e40
#define MGAREG_CODECHARDPTR 			0x3e4c
#define MGAREG_CODECHOSTPTR 			0x3e48
#define MGAREG_CODECLCODE 			0x3e50
#define MGAREG_CXBNDRY 			0x1c80

#    define CXB_cxleft_MASK 		0xfffff000 	/* bits 0-11 */
#    define CXB_cxleft_SHIFT 		0 		
#    define CXB_cxright_MASK 		0xf000ffff 	/* bits 16-27 */
#    define CXB_cxright_SHIFT 		16 		

#define MGAREG_CXLEFT 				0x1ca0
#define MGAREG_CXRIGHT 			0x1ca4
#define MGAREG_DMAMAP30 			0x1e30
#define MGAREG_DMAMAP74 			0x1e34
#define MGAREG_DMAMAPB8 			0x1e38
#define MGAREG_DMAMAPFC 			0x1e3c
#define MGAREG_DMAPAD 				0x1c54
#define MGAREG_DR0_Z32LSB 			0x2c50
#define MGAREG_DR0_Z32MSB 			0x2c54
#define MGAREG_DR2_Z32LSB 			0x2c60
#define MGAREG_DR2_Z32MSB 			0x2c64
#define MGAREG_DR3_Z32LSB 			0x2c68
#define MGAREG_DR3_Z32MSB 			0x2c6c
#define MGAREG_DR0 				0x1cc0
#define MGAREG_DR2 				0x1cc8
#define MGAREG_DR3 				0x1ccc
#define MGAREG_DR4 				0x1cd0
#define MGAREG_DR6 				0x1cd8
#define MGAREG_DR7 				0x1cdc
#define MGAREG_DR8 				0x1ce0
#define MGAREG_DR10 				0x1ce8
#define MGAREG_DR11 				0x1cec
#define MGAREG_DR12 				0x1cf0