ffb_dac.h

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						 * 0 = Local Drawing Idle
						 */
#define FFBDAC_CFG_WTCTRL_DRS	0x00000010	/* Drawing Status
						 * 1 = Network Drawing Active
						 * 0 = Network Drawing Idle
						 */

/* Transparent Mask Control Register */
#define FFBDAC_CFG_TMCTRL_OMSK	0x000000ff	/* Overlay Mask			 */

/* Transparent Color Key Register */
#define FFBDAC_CFG_TCOLORKEY_K	0x000000ff	/* Overlay Color Key		 */

/* Window Address Mask Register (PAC2 only) */
#define FFBDAC_CFG_WAMASK_PMSK	0x0000003f	/* PWLUT select PMASK		 */
#define FFBDAC_CFG_WAMASK_OMSK	0x00000300	/* OWLUT control OMASK		 */

/* (non-Overlay) Window Lookup Table Registers, PAC1 format */
#define FFBDAC_PAC1_WLUT_DB	0x00000020	/* 0 = Buffer A, 1 = Buffer B	 */
#define FFBDAC_PAC1_WLUT_C	0x0000001c	/* C: Color Model Selection	 */
#define FFBDAC_PAC1_WLUT_C_8P	0x00000000	/* C: 8bpp Pseudocolor		 */
#define FFBDAC_PAC1_WLUT_C_8LG	0x00000004	/* C: 8bpp Linear Grey		 */
#define FFBDAC_PAC1_WLUT_C_8NG	0x00000008	/* C: 8bpp Non-Linear Grey	 */
#define FFBDAC_PAC1_WLUT_C_24D	0x00000010	/* C: 24bpp Directcolor		 */
#define FFBDAC_PAC1_WLUT_C_24LT	0x00000014	/* C: 24bpp Linear Truecolor	 */
#define FFBDAC_PAC1_WLUT_C_24NT	0x00000018	/* C: 24bpp Non-Linear Truecolor */
#define FFBDAC_PAC1_WLUT_PCS	0x00000003	/* Pseudocolor Src		 */
#define FFBDAC_PAC1_WLUT_P_XO	0x00000000	/* Pseudocolor Src - XO[7:0]	 */
#define FFBDAC_PAC1_WLUT_P_R	0x00000001	/* Pseudocolor Src - R[7:0]	 */
#define FFBDAC_PAC1_WLUT_P_G	0x00000002	/* Pseudocolor Src - G[7:0]	 */
#define FFBDAC_PAC1_WLUT_P_B	0x00000003	/* Pseudocolor Src - B[7:0]	 */

/* (non-Overlay) Window Lookup Table Registers, PAC2 format */
#define FFBDAC_PAC2_WLUT_PTBL	0x00000030	/* Palette Table Entry		 */
#define FFBDAC_PAC2_WLUT_LKUP	0x00000100	/* 1 = Use palette, 0 = Bypass	 */
#define FFBDAC_PAC2_WLUT_PCS	0x00003000	/* Pseudocolor Src		 */
#define FFBDAC_PAC2_WLUT_P_XO	0x00000000	/* Pseudocolor Src - XO[7:0]	 */
#define FFBDAC_PAC2_WLUT_P_R	0x00001000	/* Pseudocolor Src - R[7:0]	 */
#define FFBDAC_PAC2_WLUT_P_G	0x00002000	/* Pseudocolor Src - G[7:0]	 */
#define FFBDAC_PAC2_WLUT_P_B	0x00003000	/* Pseudocolor Src - B[7:0]	 */
#define FFBDAC_PAC2_WLUT_DEPTH	0x00004000	/* 0 = Pseudocolor, 1 = Truecolor*/
#define FFBDAC_PAC2_WLUT_DB	0x00008000	/* 0 = Buffer A, 1 = Buffer B	 */

/* Signature Analysis Control Register */
#define FFBDAC_CFG_SANAL_SRR	0x000000ff	/* DAC Seed/Result for Red	 */
#define FFBDAC_CFG_SANAL_SRG	0x0000ff00	/* DAC Seed/Result for Green	 */
#define FFBDAC_CFG_SANAL_SRB	0x00ff0000	/* DAC Seed/Result for Blue	 */
#define FFBDAC_CFG_SANAL_RQST	0x01000000	/* Signature Capture Request	 */
#define FFBDAC_CFG_SANAL_BSY	0x02000000	/* Signature Analysis Busy	 */
#define FFBDAC_CFG_SANAL_DSM	0x04000000	/* Data Strobe Mode
						 * 0 = Signature Analysis Mode
						 * 1 = Data Strobe Mode
						 */

/* DAC Control Register */
#define FFBDAC_CFG_DACCTRL_O2	0x00000003	/* Operand 2 Select
						 * 00 = Normal Operation
						 * 01 = Select 145mv Reference
						 * 10 = Select Blue DAC Output
						 * 11 = Reserved
						 */
#define FFBDAC_CFG_DACCTRL_O1	0x0000000c	/* Operand 1 Select
						 * 00 = Normal Operation
						 * 01 = Select Green DAC Output
						 * 10 = Select Red DAC Output
						 * 11 = Reserved
						 */
#define FFBDAC_CFG_DACCTRL_CR	0x00000010	/* Comparator Result
						 * 0 = operand1 < operand2
						 * 1 = operand1 > operand2
						 */
#define FFBDAC_CFG_DACCTRL_SGE	0x00000020	/* Sync-on-Green Enable		 */
#define FFBDAC_CFG_DACCTRL_PE	0x00000040	/* Pedestal Enable		 */
#define FFBDAC_CFG_DACCTRL_VPD	0x00000080	/* VSYNC* Pin Disable		 */
#define FFBDAC_CFG_DACCTRL_SPB	0x00000100	/* Sync Polarity Bit
						 * 0 = VSYNC* and CSYNC* active low
						 * 1 = VSYNC* and CSYNC* active high
						 */

/* Timing Generator Control Register */
#define FFBDAC_CFG_TGEN_VIDE	0x00000001	/* Video Enable			 */
#define FFBDAC_CFG_TGEN_TGE	0x00000002	/* Timing Generator Enable	 */
#define FFBDAC_CFG_TGEN_HSD	0x00000004	/* HSYNC* Disabled		 */
#define FFBDAC_CFG_TGEN_VSD	0x00000008	/* VSYNC* Disabled		 */
#define FFBDAC_CFG_TGEN_EQD	0x00000010	/* Equalization Disabled	 */
#define FFBDAC_CFG_TGEN_MM	0x00000020	/* 0 = Slave, 1 = Master	 */
#define FFBDAC_CFG_TGEN_IM	0x00000040	/* 1 = Interlaced Mode		 */

/* Device Identification Register, should be 0xA236E1AD for FFB bt497/bt498 */
#define FFBDAC_CFG_DID_ONE	0x00000001	/* Always set			 */
#define FFBDAC_CFG_DID_MANUF	0x00000ffe	/* Manufacturer ID		 */
#define FFBDAC_CFG_DID_PNUM	0x0ffff000	/* Device Part Number		 */
#define FFBDAC_CFG_DID_REV	0xf0000000	/* Device Revision		 */

/* Monitor Port Data Register */
#define FFBDAC_CFG_MPDATA_SCL	0x00000001	/* SCL Data			 */
#define FFBDAC_CFG_MPDATA_SDA	0x00000002	/* SDA Data			 */

/* Monitor Port Sense Register */
#define FFBDAC_CFG_MPSENSE_SCL	0x00000001	/* SCL Sense			 */
#define FFBDAC_CFG_MPSENSE_SDA	0x00000002	/* SDA Sense			 */

/* DAC register access shorthands. */
#define DACCUR_READ(DAC, ADDR)		((DAC)->cur = (ADDR), (DAC)->curdata)
#define DACCUR_WRITE(DAC, ADDR, VAL)	((DAC)->cur = (ADDR), (DAC)->curdata = (VAL))
#define DACCFG_READ(DAC, ADDR)		((DAC)->cfg = (ADDR), (DAC)->cfgdata)
#define DACCFG_WRITE(DAC, ADDR, VAL)	((DAC)->cfg = (ADDR), (DAC)->cfgdata = (VAL))

typedef struct ffb_dac_hwstate {
	unsigned int ppllctrl;
	unsigned int gpllctrl;
	unsigned int pfctrl;
	unsigned int uctrl;
	unsigned int clut[256 * 4];	/* One 256 entry clut on PAC1, 4 on PAC2 */
	unsigned int ovluts[4];		/* Overlay WLUTS, PAC2 only */
	unsigned int wtctrl;
	unsigned int tmctrl;
	unsigned int tcolorkey;
	unsigned int wamask;
	unsigned int pwluts[64];
	unsigned int dacctrl;
	unsigned int tgen;
	unsigned int vbnp;
	unsigned int vbap;
	unsigned int vsnp;
	unsigned int vsap;
	unsigned int hsnp;
	unsigned int hbnp;
	unsigned int hbap;
	unsigned int hsyncnp;
	unsigned int hsyncap;
	unsigned int hscennp;
	unsigned int hscenap;
	unsigned int epnp;
	unsigned int einp;
	unsigned int eiap;
} ffb_dac_hwstate_t;

typedef struct {
	Bool		InUse;

	/* The following fields are undefined unless InUse is TRUE. */
	int		refcount;
	Bool		canshare;
	unsigned int	wlut_regval;
	int		buffer;		/* 0 = Buffer A, 1 = Buffer B	*/
	int		depth;		/* 8 or 32 bpp			*/
	int		greyscale;	/* 1 = greyscale, 0 = color	*/
	int		linear;		/* 1 = linear, 0 = non-linear	*/
	int		direct;		/* 1 = 24bpp directcolor	*/
	int		channel;	/* 0 = X, 1 = R, 2 = G, 3 = B	*/
	int		palette;	/* Only PAC2 has multiple CLUTs	*/
} ffb_wid_info_t;

#define FFB_MAX_PWIDS	64
typedef struct {
	int		num_wids;
	int		wid_shift;	/* To get X channel value	*/
	ffb_wid_info_t	wid_pool[FFB_MAX_PWIDS];
} ffb_wid_pool_t;

typedef struct ffb_dac_info {
	unsigned int flags;
#define FFB_DAC_PAC1	0x00000001	/* Pacifica1 DAC, BT9068	*/
#define FFB_DAC_PAC2	0x00000002	/* Pacifica2 DAC, BT498		*/
#define FFB_DAC_ICURCTL	0x00000004	/* Inverted CUR_CTRL bits	*/

	unsigned int kernel_wid;

	/* These registers need to be modified when changing DAC
	 * timing state, so at init time we capture their values.
	 */
	unsigned int ffbcfg0;
	unsigned int ffbcfg2;
	unsigned int ffb_passin_ctrl;	/* FFB2+/AFB only */

	ffb_dac_hwstate_t	kern_dac_state;
	ffb_dac_hwstate_t	x_dac_state;

	ffb_wid_pool_t		wid_table;
} ffb_dac_info_t;

#endif /* _FFB_DAC_H */