ffb_regs.h

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#define FFB_PPC_DCE_MASK	0x030000
/* Alpha blend */
#define FFB_PPC_ABE_DISABLE	0x008000
#define FFB_PPC_ABE_ENABLE	0x00c000
#define FFB_PPC_ABE_MASK	0x00c000
/* View clip */
#define FFB_PPC_VCE_DISABLE	0x001000
#define FFB_PPC_VCE_2D		0x002000
#define FFB_PPC_VCE_3D		0x003000
#define FFB_PPC_VCE_MASK	0x003000
/* Area pattern */
#define FFB_PPC_APE_DISABLE	0x000800
#define FFB_PPC_APE_ENABLE	0x000c00
#define FFB_PPC_APE_MASK	0x000c00
/* Transparent background */
#define FFB_PPC_TBE_OPAQUE	0x000200
#define FFB_PPC_TBE_TRANSPARENT	0x000300
#define FFB_PPC_TBE_MASK	0x000300
/* Z source */
#define FFB_PPC_ZS_VAR		0x000080
#define FFB_PPC_ZS_CONST	0x0000c0
#define FFB_PPC_ZS_MASK		0x0000c0
/* Y source */
#define FFB_PPC_YS_VAR		0x000020
#define FFB_PPC_YS_CONST	0x000030
#define FFB_PPC_YS_MASK		0x000030
/* X source */
#define FFB_PPC_XS_WID		0x000004
#define FFB_PPC_XS_VAR		0x000008
#define FFB_PPC_XS_CONST	0x00000c
#define FFB_PPC_XS_MASK		0x00000c
/* Color (BGR) source */
#define FFB_PPC_CS_VAR		0x000002
#define FFB_PPC_CS_CONST	0x000003
#define FFB_PPC_CS_MASK		0x000003

/* X Clip */
#define FFB_XCLIP_XREF		0x000000ff
#define FFB_XCLIP_TEST_MASK	0x00070000
#define FFB_XCLIP_TEST_ALWAYS	0x00000000
#define FFB_XCLIP_TEST_GT	0x00010000
#define FFB_XCLIP_TEST_EQ	0x00020000
#define FFB_XCLIP_TEST_GE	0x00030000
#define FFB_XCLIP_TEST_NEVER	0x00040000
#define FFB_XCLIP_TEST_LE	0x00050000
#define FFB_XCLIP_TEST_NE	0x00060000
#define FFB_XCLIP_TEST_LT	0x00070000

/* FB Control register */
/* Write buffer dest */
#define FFB_FBC_WB_A		0x20000000
#define FFB_FBC_WB_B		0x40000000
#define FFB_FBC_WB_AB		0x60000000
#define FFB_FBC_WB_C		0x80000000
#define FFB_FBC_WB_AC		0xa0000000
#define FFB_FBC_WB_BC		0xc0000000
#define FFB_FBC_WB_ABC		0xe0000000
#define FFB_FBC_WB_MASK		0xe0000000
/* Write enable */
#define FFB_FBC_WE_FORCEOFF	0x00100000
#define FFB_FBC_WE_FORCEON	0x00200000
#define FFB_FBC_WE_USE_WMASK	0x00300000
#define FFB_FBC_WE_MASK		0x00300000
/* Write group mode */
#define FFB_FBC_WM_RSVD		0x00040000
#define FFB_FBC_WM_COMBINED	0x00080000
#define FFB_FBC_WM_SEPARATE	0x000c0000
#define FFB_FBC_WM_MASK		0x000c0000
/* Read buffer src */
#define FFB_FBC_RB_A		0x00004000
#define FFB_FBC_RB_B		0x00008000
#define FFB_FBC_RB_C		0x0000c000
#define FFB_FBC_RB_MASK		0x0000c000
/* Stereo buf dest */
#define FFB_FBC_SB_LEFT		0x00001000
#define FFB_FBC_SB_RIGHT	0x00002000
#define FFB_FBC_SB_BOTH		0x00003000
#define FFB_FBC_SB_MASK		0x00003000
/* Z plane group enable */
#define FFB_FBC_ZE_OFF		0x00000400
#define FFB_FBC_ZE_ON		0x00000800
#define FFB_FBC_ZE_MASK		0x00000c00
/* Y plane group enable */
#define FFB_FBC_YE_OFF		0x00000100
#define FFB_FBC_YE_ON		0x00000200
#define FFB_FBC_YE_MASK		0x00000300
/* X plane group enable */
#define FFB_FBC_XE_OFF		0x00000040
#define FFB_FBC_XE_ON		0x00000080
#define FFB_FBC_XE_MASK		0x000000c0
/* B plane group enable */
#define FFB_FBC_BE_OFF		0x00000010
#define FFB_FBC_BE_ON		0x00000020
#define FFB_FBC_BE_MASK		0x00000030
/* G plane group enable */
#define FFB_FBC_GE_OFF		0x00000004
#define FFB_FBC_GE_ON		0x00000008
#define FFB_FBC_GE_MASK		0x0000000c
/* R plane group enable */
#define FFB_FBC_RE_OFF		0x00000001
#define FFB_FBC_RE_ON		0x00000002
#define FFB_FBC_RE_MASK		0x00000003
/* Combined */
#define FFB_FBC_RGBE_OFF	0x00000015
#define FFB_FBC_RGBE_ON		0x0000002a
#define FFB_FBC_RGBE_MASK	0x0000003f

/* Raster OP */
#define FFB_ROP_YZ_MASK		0x008f0000
#define FFB_ROP_X_MASK		0x00008f00
#define FFB_ROP_RGB_MASK	0x0000008f

/* Now the rops themselves which get shifted into the
 * above fields.
 */
#define FFB_ROP_EDIT_BIT	0x80
#define FFB_ROP_ZERO		0x80
#define FFB_ROP_NEW_AND_OLD	0x81
#define FFB_ROP_NEW_AND_NOLD	0x82
#define FFB_ROP_NEW		0x83
#define FFB_ROP_NNEW_AND_OLD	0x84
#define FFB_ROP_OLD		0x85
#define FFB_ROP_NEW_XOR_OLD	0x86
#define FFB_ROP_NEW_OR_OLD	0x87
#define FFB_ROP_NNEW_AND_NOLD	0x88
#define FFB_ROP_NNEW_XOR_NOLD	0x89
#define FFB_ROP_NOLD		0x8a
#define FFB_ROP_NEW_OR_NOLD	0x8b
#define FFB_ROP_NNEW		0x8c
#define FFB_ROP_NNEW_OR_OLD	0x8d
#define FFB_ROP_NNEW_OR_NOLD	0x8e
#define FFB_ROP_ONES		0x8f

/* FB Compare */
#define FFB_CMP_MATCHC_MASK	0x8f000000
#define FFB_CMP_MAGNC_MASK	0x00870000
#define FFB_CMP_MATCHAB_MASK	0x0000ff00
#define FFB_CMP_MAGNAB_MASK	0x000000ff

/* Compare Match codes */
#define FFB_CMP_MATCH_EDIT_BIT	0x80
#define FFB_CMP_MATCH_ALWAYS	0x80
#define FFB_CMP_MATCH_NEVER	0x81
#define FFB_CMP_MATCH_EQ	0x82
#define FFB_CMP_MATCH_NE	0x83
#define FFB_CMP_MATCH_A_ALWAYS	0xc0
#define FFB_CMP_MATCH_B_ALWAYS	0xa0

/* Compare Magnitude codes */
#define FFB_CMP_MAGN_EDIT_BIT	0x80
#define FFB_CMP_MAGN_ALWAYS	0x80
#define FFB_CMP_MAGN_GT		0x81
#define FFB_CMP_MAGN_EQ		0x82
#define FFB_CMP_MAGN_GE		0x83
#define FFB_CMP_MAGN_NEVER	0x84
#define FFB_CMP_MAGN_LE		0x85
#define FFB_CMP_MAGN_NE		0x86
#define FFB_CMP_MAGN_LT		0x87
#define FFB_CMP_MAGN_A_ALWAYS	0xc0
#define FFB_CMP_MAGN_B_ALWAYS	0xa0

/* User Control and Status */
#define FFB_UCSR_FIFO_MASK	0x00000fff
#define FFB_UCSR_PICK_NO_HIT	0x00020000
#define FFB_UCSR_PICK_HIT	0x00030000
#define FFB_UCSR_PICK_DISABLE	0x00080000
#define FFB_UCSR_PICK_ENABLE	0x000c0000
#define FFB_UCSR_FB_BUSY	0x01000000
#define FFB_UCSR_RP_BUSY	0x02000000
#define FFB_UCSR_ALL_BUSY	(FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
#define FFB_UCSR_READ_ERR	0x40000000
#define FFB_UCSR_FIFO_OVFL	0x80000000
#define FFB_UCSR_ALL_ERRORS	(FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)

/* Mode Enable Register */
#define FFB_MER_EIRA		0x00000080 /* Enable read-ahead, increasing */
#define FFB_MER_EDRA		0x000000c0 /* Enable read-ahead, decreasing */
#define FFB_MER_DRA		0x00000040 /* No read-ahead */

/* FBram Config 0 */
#define FFB_FBCFG0_RFTIME	0xff800000
#define FFB_FBCFG0_XMAX		0x007c0000
#define FFB_FBCFG0_YMAX		0x0003ffc0
#define FFB_FBCFG0_RES_MASK	0x00000030
#define FFB_FBCFG0_RES_HIGH	0x00000030 /* 1920x1360 */
#define FFB_FBCFG0_RES_STD	0x00000020 /* 1280x1024 */
#define FFB_FBCFG0_RES_STEREO	0x00000010 /* 960x580 */
#define FFB_FBCFG0_RES_PRTRAIT	0x00000000 /* 1280x2048 */
#define FFB_FBCFG0_ITRLACE	0x00000000
#define FFB_FBCFG0_SEQUENTIAL	0x00000008
#define FFB_FBCFG0_DRENA	0x00000004
#define FFB_FBCFG0_BPMODE	0x00000002
#define FFB_FBCFG0_RFRSH_RST	0x00000001

typedef struct _ffb_dac {
	volatile unsigned int	cfg;
	volatile unsigned int	cfgdata;
	volatile unsigned int	cur;
	volatile unsigned int	curdata;
} ffb_dac, *ffb_dacPtr;

/* Writing 2 32-bit registers at a time using 64-bit stores. -DaveM */
#if defined(__GNUC__) && defined(USE_VIS)
/* 64-bit register writing support.
 * Note: "lo" means "low address".
 */
#define FFB_WRITE64_COMMON(__regp, __lo32, __hi32, REG0, REG1) \
do {	__extension__ register unsigned int __r0 __asm__(""#REG0); \
	__extension__ register unsigned int __r1 __asm__(""#REG1); \
	__r0 = (__lo32); \
	__r1 = (__hi32); \
	__asm__ __volatile__ ("sllx\t%0, 32, %%g1\n\t" \
			      "srl\t%1, 0, %1\n\t" \
			      "or\t%%g1, %1, %%g1\n\t" \
			      "stx\t%%g1, %2" \
	 : : "r" (__r0), "r" (__r1), "m" (*(__regp)) : "g1"); \
} while(0)

#define FFB_WRITE64P(__regp, __srcp) \
do {	__asm__ __volatile__ ("ldx\t%0, %%g2;" \
			      "stx\t%%g2, %1" \
	 : : "m" (*(__srcp)), "m" (*(__regp)) \
         : "g2"); \
} while(0)			      

#define FFB_WRITE64(__regp, __lo32, __hi32) \
	FFB_WRITE64_COMMON(__regp, __lo32, __hi32, g2, g3)
#define FFB_WRITE64_2(__regp, __lo32, __hi32) \
	FFB_WRITE64_COMMON(__regp, __lo32, __hi32, g4, g5)
#define FFB_WRITE64_3(__regp, __lo32, __hi32) \
	FFB_WRITE64_COMMON(__regp, __lo32, __hi32, o4, o5)

#else /* Do not use 64-bit writes. */

#define FFB_WRITE64(__regp, __lo32, __hi32) \
do {	volatile unsigned int *__p = (__regp); \
	*__p = (__lo32); \
	*(__p + 1) = (__hi32); \
} while(0)

#define FFB_WRITE64P(__regp, __srcp) \
do {	volatile unsigned int *__p = (__regp); \
	unsigned int *__q = (__srcp); \
	*__p = *__q; \
	*(__p + 1) = *(__q + 1); \
} while(0)

#define FFB_WRITE64_2(__regp, __lo32, __hi32) \
	FFB_WRITE64(__regp, __lo32, __hi32)
#define FFB_WRITE64_3(__regp, __lo32, __hi32) \
	FFB_WRITE64(__regp, __lo32, __hi32)
#endif

#endif /* FFBREGS_H */