📄 r128_reg.h
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#define R128_PALETTE_INDEX 0x00b0#define R128_PC_DEBUG_MODE 0x1760#define R128_PC_GUI_CTLSTAT 0x1748#define R128_PC_GUI_MODE 0x1744# define R128_PC_IGNORE_UNIFY (1 << 5)#define R128_PC_MISC_CNTL 0x0188#define R128_PC_NGUI_CTLSTAT 0x0184# define R128_PC_FLUSH_GUI (3 << 0)# define R128_PC_RI_GUI (1 << 2)# define R128_PC_FLUSH_ALL 0x00ff# define R128_PC_BUSY (1 << 31)#define R128_PC_NGUI_MODE 0x0180#define R128_PCI_GART_PAGE 0x017c#define R128_PLANE_3D_MASK_C 0x1d44#define R128_PLL_TEST_CNTL 0x0013 /* PLL */#define R128_PMI_CAP_ID 0x0f5c /* PCI */#define R128_PMI_DATA 0x0f63 /* PCI */#define R128_PMI_NXT_CAP_PTR 0x0f5d /* PCI */#define R128_PMI_PMC_REG 0x0f5e /* PCI */#define R128_PMI_PMCSR_REG 0x0f60 /* PCI */#define R128_PMI_REGISTER 0x0f5c /* PCI */#define R128_PPLL_CNTL 0x0002 /* PLL */# define R128_PPLL_RESET (1 << 0)# define R128_PPLL_SLEEP (1 << 1)# define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16)# define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)#define R128_PPLL_DIV_0 0x0004 /* PLL */#define R128_PPLL_DIV_1 0x0005 /* PLL */#define R128_PPLL_DIV_2 0x0006 /* PLL */#define R128_PPLL_DIV_3 0x0007 /* PLL */# define R128_PPLL_FB3_DIV_MASK 0x07ff# define R128_PPLL_POST3_DIV_MASK 0x00070000#define R128_PPLL_REF_DIV 0x0003 /* PLL */# define R128_PPLL_REF_DIV_MASK 0x03ff# define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */# define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */#define R128_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */#define R128_REG_BASE 0x0f18 /* PCI */#define R128_REGPROG_INF 0x0f09 /* PCI */#define R128_REVISION_ID 0x0f08 /* PCI */#define R128_SC_BOTTOM 0x164c#define R128_SC_BOTTOM_RIGHT 0x16f0#define R128_SC_BOTTOM_RIGHT_C 0x1c8c#define R128_SC_LEFT 0x1640#define R128_SC_RIGHT 0x1644#define R128_SC_TOP 0x1648#define R128_SC_TOP_LEFT 0x16ec#define R128_SC_TOP_LEFT_C 0x1c88#define R128_SEQ8_DATA 0x03c5 /* VGA */#define R128_SEQ8_IDX 0x03c4 /* VGA */#define R128_SNAPSHOT_F_COUNT 0x0244#define R128_SNAPSHOT_VH_COUNTS 0x0240#define R128_SNAPSHOT_VIF_COUNT 0x024c#define R128_SRC_OFFSET 0x15ac#define R128_SRC_PITCH 0x15b0#define R128_SRC_PITCH_OFFSET 0x1428#define R128_SRC_SC_BOTTOM 0x165c#define R128_SRC_SC_BOTTOM_RIGHT 0x16f4#define R128_SRC_SC_RIGHT 0x1654#define R128_SRC_X 0x1414#define R128_SRC_X_Y 0x1590#define R128_SRC_Y 0x1418#define R128_SRC_Y_X 0x1434#define R128_STATUS 0x0f06 /* PCI */#define R128_SUBPIC_CNTL 0x0540 /* ? */#define R128_SUB_CLASS 0x0f0a /* PCI */#define R128_SURFACE_DELAY 0x0b00#define R128_SURFACE0_INFO 0x0b0c#define R128_SURFACE0_LOWER_BOUND 0x0b04#define R128_SURFACE0_UPPER_BOUND 0x0b08#define R128_SURFACE1_INFO 0x0b1c#define R128_SURFACE1_LOWER_BOUND 0x0b14#define R128_SURFACE1_UPPER_BOUND 0x0b18#define R128_SURFACE2_INFO 0x0b2c#define R128_SURFACE2_LOWER_BOUND 0x0b24#define R128_SURFACE2_UPPER_BOUND 0x0b28#define R128_SURFACE3_INFO 0x0b3c#define R128_SURFACE3_LOWER_BOUND 0x0b34#define R128_SURFACE3_UPPER_BOUND 0x0b38#define R128_SW_SEMAPHORE 0x013c#define R128_TEST_DEBUG_CNTL 0x0120#define R128_TEST_DEBUG_MUX 0x0124#define R128_TEST_DEBUG_OUT 0x012c#define R128_TMDS_CRC 0x02a0#define R128_TMDS_TRANSMITTER_CNTL 0x02a4# define R128_TMDS_PLLEN (1 << 0)# define R128_TMDS_PLLRST (1 << 1)#define R128_TRAIL_BRES_DEC 0x1614#define R128_TRAIL_BRES_ERR 0x160c#define R128_TRAIL_BRES_INC 0x1610#define R128_TRAIL_X 0x1618#define R128_TRAIL_X_SUB 0x1620#define R128_VCLK_ECP_CNTL 0x0008 /* PLL */#define R128_VENDOR_ID 0x0f00 /* PCI */#define R128_VGA_DDA_CONFIG 0x02e8#define R128_VGA_DDA_ON_OFF 0x02ec#define R128_VID_BUFFER_CONTROL 0x0900#define R128_VIDEOMUX_CNTL 0x0190#define R128_VIPH_CONTROL 0x01D0 /* ? */#define R128_WAIT_UNTIL 0x1720#define R128_X_MPLL_REF_FB_DIV 0x000a /* PLL */#define R128_XCLK_CNTL 0x000d /* PLL */#define R128_XDLL_CNTL 0x000c /* PLL */#define R128_XPLL_CNTL 0x000b /* PLL */ /* Registers for CCE and Microcode Engine */#define R128_PM4_MICROCODE_ADDR 0x07d4#define R128_PM4_MICROCODE_RADDR 0x07d8#define R128_PM4_MICROCODE_DATAH 0x07dc#define R128_PM4_MICROCODE_DATAL 0x07e0#define R128_PM4_BUFFER_OFFSET 0x0700#define R128_PM4_BUFFER_CNTL 0x0704# define R128_PM4_NONPM4 (0 << 28)# define R128_PM4_192PIO (1 << 28)# define R128_PM4_192BM (2 << 28)# define R128_PM4_128PIO_64INDBM (3 << 28)# define R128_PM4_128BM_64INDBM (4 << 28)# define R128_PM4_64PIO_128INDBM (5 << 28)# define R128_PM4_64BM_128INDBM (6 << 28)# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)#define R128_PM4_BUFFER_WM_CNTL 0x0708# define R128_WMA_SHIFT 0# define R128_WMB_SHIFT 8# define R128_WMC_SHIFT 16# define R128_WB_WM_SHIFT 24#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c#define R128_PM4_BUFFER_DL_RPTR 0x0710#define R128_PM4_BUFFER_DL_WPTR 0x0714# define R128_PM4_BUFFER_DL_DONE (1 << 31)#define R128_PM4_BUFFER_DL_WPTR_DELAY 0x0718# define R128_PRE_WRITE_TIMER_SHIFT 0# define R128_PRE_WRITE_LIMIT_SHIFT 23#define R128_PM4_VC_FPU_SETUP 0x071c# define R128_FRONT_DIR_CW (0 << 0)# define R128_FRONT_DIR_CCW (1 << 0)# define R128_FRONT_DIR_MASK (1 << 0)# define R128_BACKFACE_CULL (0 << 1)# define R128_BACKFACE_POINTS (1 << 1)# define R128_BACKFACE_LINES (2 << 1)# define R128_BACKFACE_SOLID (3 << 1)# define R128_BACKFACE_MASK (3 << 1)# define R128_FRONTFACE_CULL (0 << 3)# define R128_FRONTFACE_POINTS (1 << 3)# define R128_FRONTFACE_LINES (2 << 3)# define R128_FRONTFACE_SOLID (3 << 3)# define R128_FRONTFACE_MASK (3 << 3)# define R128_FPU_COLOR_SOLID (0 << 5)# define R128_FPU_COLOR_FLAT (1 << 5)# define R128_FPU_COLOR_GOURAUD (2 << 5)# define R128_FPU_COLOR_GOURAUD2 (3 << 5)# define R128_FPU_COLOR_MASK (3 << 5)# define R128_FPU_SUB_PIX_2BITS (0 << 7)# define R128_FPU_SUB_PIX_4BITS (1 << 7)# define R128_FPU_MODE_2D (0 << 8)# define R128_FPU_MODE_3D (1 << 8)# define R128_TRAP_BITS_DISABLE (1 << 9)# define R128_EDGE_ANTIALIAS (1 << 10)# define R128_SUPERSAMPLE (1 << 11)# define R128_XFACTOR_2 (0 << 12)# define R128_XFACTOR_4 (1 << 12)# define R128_YFACTOR_2 (0 << 13)# define R128_YFACTOR_4 (1 << 13)# define R128_FLAT_SHADE_VERTEX_D3D (0 << 14)# define R128_FLAT_SHADE_VERTEX_OGL (1 << 14)# define R128_FPU_ROUND_TRUNCATE (0 << 15)# define R128_FPU_ROUND_NEAREST (1 << 15)# define R128_WM_SEL_8DW (0 << 16)# define R128_WM_SEL_16DW (1 << 16)# define R128_WM_SEL_32DW (2 << 16)#define R128_PM4_VC_DEBUG_CONFIG 0x07a4#define R128_PM4_VC_STAT 0x07a8#define R128_PM4_VC_TIMESTAMP0 0x07b0#define R128_PM4_VC_TIMESTAMP1 0x07b4#define R128_PM4_STAT 0x07b8# define R128_PM4_FIFOCNT_MASK 0x0fff# define R128_PM4_BUSY (1 << 16)# define R128_PM4_GUI_ACTIVE (1 << 31)#define R128_PM4_BUFFER_ADDR 0x07f0#define R128_PM4_MICRO_CNTL 0x07fc# define R128_PM4_MICRO_FREERUN (1 << 30)#define R128_PM4_FIFO_DATA_EVEN 0x1000#define R128_PM4_FIFO_DATA_ODD 0x1004#define R128_SCALE_3D_CNTL 0x1a00# define R128_SCALE_DITHER_ERR_DIFF (0 << 1)# define R128_SCALE_DITHER_TABLE (1 << 1)# define R128_TEX_CACHE_SIZE_FULL (0 << 2)# define R128_TEX_CACHE_SIZE_HALF (1 << 2)# define R128_DITHER_INIT_CURR (0 << 3)# define R128_DITHER_INIT_RESET (1 << 3)# define R128_ROUND_24BIT (1 << 4)# define R128_TEX_CACHE_DISABLE (1 << 5)# define R128_SCALE_3D_NOOP (0 << 6)# define R128_SCALE_3D_SCALE (1 << 6)# define R128_SCALE_3D_TEXMAP_SHADE (2 << 6)# define R128_SCALE_PIX_BLEND (0 << 8)# define R128_SCALE_PIX_REPLICATE (1 << 8)# define R128_TEX_CACHE_SPLIT (1 << 9)# define R128_APPLE_YUV_MODE (1 << 10)# define R128_TEX_CACHE_PALLETE_MODE (1 << 11)# define R128_ALPHA_COMB_ADD_CLAMP (0 << 12)# define R128_ALPHA_COMB_ADD_NCLAMP (1 << 12)# define R128_ALPHA_COMB_SUB_SRC_DST_CLAMP (2 << 12)# define R128_ALPHA_COMB_SUB_SRC_DST_NCLAMP (3 << 12)# define R128_ALPHA_COMB_FCN_MASK (3 << 12)# define R128_FOG_VERTEX (0 << 14)# define R128_FOG_TABLE (1 << 14)# define R128_SIGNED_DST_CLAMP (1 << 15)# define R128_ALPHA_BLEND_ZERO (0 )# define R128_ALPHA_BLEND_ONE (1 )# define R128_ALPHA_BLEND_SRCCOLOR (2 )# define R128_ALPHA_BLEND_INVSRCCOLOR (3 )# define R128_ALPHA_BLEND_SRCALPHA (4 )# define R128_ALPHA_BLEND_INVSRCALPHA (5 )# define R128_ALPHA_BLEND_DSTALPHA (6 )# define R128_ALPHA_BLEND_INVDSTALPHA (7 )# define R128_ALPHA_BLEND_DSTCOLOR (8 )# define R128_ALPHA_BLEND_INVDSTCOLOR (9 )# define R128_ALPHA_BLEND_SAT (10) /* aka SRCALPHASAT */# define R128_ALPHA_BLEND_BLEND (11) /* aka BOTHSRCALPHA */# define R128_ALPHA_BLEND_INVBLEND (12) /* aka BOTHINVSRCALPHA */# define R128_ALPHA_BLEND_MASK (15)# define R128_ALPHA_BLEND_SRC_SHIFT (16)# define R128_ALPHA_BLEND_DST_SHIFT (20)# define R128_ALPHA_TEST_NEVER (0 << 24)# define R128_ALPHA_TEST_LESS (1 << 24)# define R128_ALPHA_TEST_LESSEQUAL (2 << 24)# define R128_ALPHA_TEST_EQUAL (3 << 24)# define R128_ALPHA_TEST_GREATEREQUAL (4 << 24)# define R128_ALPHA_TEST_GREATER (5 << 24)# define R128_ALPHA_TEST_NEQUAL (6 << 24)# define R128_ALPHA_TEST_ALWAYS (7 << 24)# define R128_ALPHA_TEST_MASK (7 << 24)# define R128_COMPOSITE_SHADOW_CMP_EQUAL (0 << 28)# define R128_COMPOSITE_SHADOW_CMP_NEQUAL (1 << 28)# define R128_COMPOSITE_SHADOW (1 << 29)# define R128_TEX_MAP_ALPHA_IN_TEXTURE (1 << 30)# define R128_TEX_CACHE_LINE_SIZE_8QW (0 << 31)# define R128_TEX_CACHE_LINE_SIZE_4QW (1 << 31)#define R128_SCALE_3D_DATATYPE 0x1a20#define R128_SETUP_CNTL 0x1bc4# define R128_DONT_START_TRIANGLE (1 << 0)
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