r128_reg.h

Mesa is an open-source implementation of the OpenGL specification - a system for rendering interacti

#       define R128_HORZ_AUTO_RATIO_FIX_EN   (1      << 31)

#define R128_FP_PANEL_CNTL                0x0288
#       define R128_FP_DIGON              (1 << 0)
#       define R128_FP_BLON               (1 << 1)
#define R128_FP_V_SYNC_STRT_WID           0x02c8
#define R128_FP_VERT_STRETCH              0x0290
#       define R128_VERT_PANEL_SIZE          (0x7ff <<  0)
#       define R128_VERT_PANEL_SHIFT         0
#       define R128_VERT_STRETCH_RATIO_MASK  0x3ff
#       define R128_VERT_STRETCH_RATIO_SHIFT 11
#       define R128_VERT_STRETCH_RATIO_MAX   1024
#       define R128_VERT_STRETCH_ENABLE      (1     << 24)
#       define R128_VERT_STRETCH_LINEREP     (0     << 25)
#       define R128_VERT_STRETCH_BLEND       (1     << 25)
#       define R128_VERT_AUTO_RATIO_EN       (1     << 26)
#       define R128_VERT_STRETCH_RESERVED    0xf8e00000

#define R128_GEN_INT_CNTL                 0x0040
#define R128_GEN_INT_STATUS               0x0044
#       define R128_VSYNC_INT_AK          (1 <<  2)
#       define R128_VSYNC_INT             (1 <<  2)
#define R128_GEN_RESET_CNTL               0x00f0
#       define R128_SOFT_RESET_GUI          (1 <<  0)
#       define R128_SOFT_RESET_VCLK         (1 <<  8)
#       define R128_SOFT_RESET_PCLK         (1 <<  9)
#       define R128_SOFT_RESET_DISPENG_XCLK (1 << 11)
#       define R128_SOFT_RESET_MEMCTLR_XCLK (1 << 12)
#define R128_GENENB                       0x03c3 /* VGA */
#define R128_GENFC_RD                     0x03ca /* VGA */
#define R128_GENFC_WT                     0x03da /* VGA, 0x03ba */
#define R128_GENMO_RD                     0x03cc /* VGA */
#define R128_GENMO_WT                     0x03c2 /* VGA */
#define R128_GENS0                        0x03c2 /* VGA */
#define R128_GENS1                        0x03da /* VGA, 0x03ba */
#define R128_GPIO_MONID                   0x0068
#       define R128_GPIO_MONID_A_0        (1 <<  0)
#       define R128_GPIO_MONID_A_1        (1 <<  1)
#       define R128_GPIO_MONID_A_2        (1 <<  2)
#       define R128_GPIO_MONID_A_3        (1 <<  3)
#       define R128_GPIO_MONID_Y_0        (1 <<  8)
#       define R128_GPIO_MONID_Y_1        (1 <<  9)
#       define R128_GPIO_MONID_Y_2        (1 << 10)
#       define R128_GPIO_MONID_Y_3        (1 << 11)
#       define R128_GPIO_MONID_EN_0       (1 << 16)
#       define R128_GPIO_MONID_EN_1       (1 << 17)
#       define R128_GPIO_MONID_EN_2       (1 << 18)
#       define R128_GPIO_MONID_EN_3       (1 << 19)
#       define R128_GPIO_MONID_MASK_0     (1 << 24)
#       define R128_GPIO_MONID_MASK_1     (1 << 25)
#       define R128_GPIO_MONID_MASK_2     (1 << 26)
#       define R128_GPIO_MONID_MASK_3     (1 << 27)
#define R128_GPIO_MONIDB                  0x006c
#define R128_GRPH8_DATA                   0x03cf /* VGA */
#define R128_GRPH8_IDX                    0x03ce /* VGA */
#define R128_GUI_DEBUG0                   0x16a0
#define R128_GUI_DEBUG1                   0x16a4
#define R128_GUI_DEBUG2                   0x16a8
#define R128_GUI_DEBUG3                   0x16ac
#define R128_GUI_DEBUG4                   0x16b0
#define R128_GUI_DEBUG5                   0x16b4
#define R128_GUI_DEBUG6                   0x16b8
#define R128_GUI_PROBE                    0x16bc
#define R128_GUI_SCRATCH_REG0             0x15e0
#define R128_GUI_SCRATCH_REG1             0x15e4
#define R128_GUI_SCRATCH_REG2             0x15e8
#define R128_GUI_SCRATCH_REG3             0x15ec
#define R128_GUI_SCRATCH_REG4             0x15f0
#define R128_GUI_SCRATCH_REG5             0x15f4
#define R128_GUI_STAT                     0x1740
#       define R128_GUI_FIFOCNT_MASK      0x0fff
#       define R128_GUI_ACTIVE            (1 << 31)

#define R128_HEADER                       0x0f0e /* PCI */
#define R128_HOST_DATA0                   0x17c0
#define R128_HOST_DATA1                   0x17c4
#define R128_HOST_DATA2                   0x17c8
#define R128_HOST_DATA3                   0x17cc
#define R128_HOST_DATA4                   0x17d0
#define R128_HOST_DATA5                   0x17d4
#define R128_HOST_DATA6                   0x17d8
#define R128_HOST_DATA7                   0x17dc
#define R128_HOST_DATA_LAST               0x17e0
#define R128_HOST_PATH_CNTL               0x0130
#define R128_HTOTAL_CNTL                  0x0009 /* PLL */
#define R128_HW_DEBUG                     0x0128
#define R128_HW_DEBUG2                    0x011c

#define R128_I2C_CNTL_1                   0x0094 /* ? */
#define R128_INTERRUPT_LINE               0x0f3c /* PCI */
#define R128_INTERRUPT_PIN                0x0f3d /* PCI */
#define R128_IO_BASE                      0x0f14 /* PCI */

#define R128_LATENCY                      0x0f0d /* PCI */
#define R128_LEAD_BRES_DEC                0x1608
#define R128_LEAD_BRES_ERR                0x1600
#define R128_LEAD_BRES_INC                0x1604
#define R128_LEAD_BRES_LNTH               0x161c
#define R128_LEAD_BRES_LNTH_SUB           0x1624
#define R128_LVDS_GEN_CNTL                0x02d0
#       define R128_LVDS_ON               (1   <<  0)
#       define R128_LVDS_DISPLAY_DIS      (1   <<  1)
#       define R128_LVDS_EN               (1   <<  7)
#       define R128_LVDS_DIGON            (1   << 18)
#       define R128_LVDS_BLON             (1   << 19)
#       define R128_LVDS_SEL_CRTC2        (1   << 23)
#       define R128_HSYNC_DELAY_SHIFT     28
#       define R128_HSYNC_DELAY_MASK      (0xf << 28)

#define R128_MAX_LATENCY                  0x0f3f /* PCI */
#define R128_MCLK_CNTL                    0x000f /* PLL */
#       define R128_FORCE_GCP             (1 << 16)
#       define R128_FORCE_PIPE3D_CP       (1 << 17)
#       define R128_FORCE_RCP             (1 << 18)
#define R128_MDGPIO_A_REG                 0x01ac
#define R128_MDGPIO_EN_REG                0x01b0
#define R128_MDGPIO_MASK                  0x0198
#define R128_MDGPIO_Y_REG                 0x01b4
#define R128_MEM_ADDR_CONFIG              0x0148
#define R128_MEM_BASE                     0x0f10 /* PCI */
#define R128_MEM_CNTL                     0x0140
#define R128_MEM_INIT_LAT_TIMER           0x0154
#define R128_MEM_INTF_CNTL                0x014c
#define R128_MEM_SDRAM_MODE_REG           0x0158
#define R128_MEM_STR_CNTL                 0x0150
#define R128_MEM_VGA_RP_SEL               0x003c
#define R128_MEM_VGA_WP_SEL               0x0038
#define R128_MIN_GRANT                    0x0f3e /* PCI */
#define R128_MM_DATA                      0x0004
#define R128_MM_INDEX                     0x0000
#define R128_MPLL_CNTL                    0x000e /* PLL */
#define R128_MPP_TB_CONFIG                0x01c0 /* ? */
#define R128_MPP_GP_CONFIG                0x01c8 /* ? */

#define R128_N_VIF_COUNT                  0x0248

#define R128_OVR_CLR                      0x0230
#define R128_OVR_WID_LEFT_RIGHT           0x0234
#define R128_OVR_WID_TOP_BOTTOM           0x0238

/* first overlay unit (there is only one) */

#define R128_OV0_Y_X_START                0x0400
#define R128_OV0_Y_X_END                  0x0404
#define R128_OV0_EXCLUSIVE_HORZ           0x0408
#       define  R128_EXCL_HORZ_START_MASK        0x000000ff
#       define  R128_EXCL_HORZ_END_MASK          0x0000ff00
#       define  R128_EXCL_HORZ_BACK_PORCH_MASK   0x00ff0000
#       define  R128_EXCL_HORZ_EXCLUSIVE_EN      0x80000000
#define R128_OV0_EXCLUSIVE_VERT           0x040C
#       define  R128_EXCL_VERT_START_MASK        0x000003ff
#       define  R128_EXCL_VERT_END_MASK          0x03ff0000
#define R128_OV0_REG_LOAD_CNTL            0x0410
#       define  R128_REG_LD_CTL_LOCK                 0x00000001L
#       define  R128_REG_LD_CTL_VBLANK_DURING_LOCK   0x00000002L
#       define  R128_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
#       define  R128_REG_LD_CTL_LOCK_READBACK        0x00000008L
#define R128_OV0_SCALE_CNTL               0x0420
#       define  R128_SCALER_PIX_EXPAND           0x00000001L
#       define  R128_SCALER_Y2R_TEMP             0x00000002L
#       define  R128_SCALER_HORZ_PICK_NEAREST    0x00000003L
#       define  R128_SCALER_VERT_PICK_NEAREST    0x00000004L
#       define  R128_SCALER_SIGNED_UV            0x00000010L
#       define  R128_SCALER_GAMMA_SEL_MASK       0x00000060L
#       define  R128_SCALER_GAMMA_SEL_BRIGHT     0x00000000L
#       define  R128_SCALER_GAMMA_SEL_G22        0x00000020L
#       define  R128_SCALER_GAMMA_SEL_G18        0x00000040L
#       define  R128_SCALER_GAMMA_SEL_G14        0x00000060L
#       define  R128_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
#       define  R128_SCALER_SURFAC_FORMAT        0x00000f00L
#       define  R128_SCALER_SOURCE_15BPP         0x00000300L
#       define  R128_SCALER_SOURCE_16BPP         0x00000400L
#       define  R128_SCALER_SOURCE_32BPP         0x00000600L
#       define  R128_SCALER_SOURCE_YUV9          0x00000900L
#       define  R128_SCALER_SOURCE_YUV12         0x00000A00L
#       define  R128_SCALER_SOURCE_VYUY422       0x00000B00L
#       define  R128_SCALER_SOURCE_YVYU422       0x00000C00L
#       define  R128_SCALER_SMART_SWITCH         0x00008000L
#       define  R128_SCALER_BURST_PER_PLANE      0x00ff0000L
#       define  R128_SCALER_DOUBLE_BUFFER        0x01000000L
#       define  R128_SCALER_DIS_LIMIT            0x08000000L
#       define  R128_SCALER_PRG_LOAD_START       0x10000000L
#       define  R128_SCALER_INT_EMU              0x20000000L
#       define  R128_SCALER_ENABLE               0x40000000L
#       define  R128_SCALER_SOFT_RESET           0x80000000L
#define R128_OV0_V_INC                    0x0424
#define R128_OV0_P1_V_ACCUM_INIT          0x0428
#       define  R128_OV0_P1_MAX_LN_IN_PER_LN_OUT        0x00000003L
#       define  R128_OV0_P1_V_ACCUM_INIT_MASK           0x01ff8000L
#define R128_OV0_P23_V_ACCUM_INIT         0x042C
#define R128_OV0_P1_BLANK_LINES_AT_TOP    0x0430
#       define  R128_P1_BLNK_LN_AT_TOP_M1_MASK   0x00000fffL
#       define  R128_P1_ACTIVE_LINES_M1          0x0fff0000L
#define R128_OV0_P23_BLANK_LINES_AT_TOP   0x0434
#       define  R128_P23_BLNK_LN_AT_TOP_M1_MASK  0x000007ffL
#       define  R128_P23_ACTIVE_LINES_M1         0x07ff0000L
#define R128_OV0_VID_BUF0_BASE_ADRS       0x0440
#       define  R128_VIF_BUF0_PITCH_SEL          0x00000001L
#       define  R128_VIF_BUF0_TILE_ADRS          0x00000002L
#       define  R128_VIF_BUF0_BASE_ADRS_MASK     0x03fffff0L
#       define  R128_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF1_BASE_ADRS       0x0444
#       define  R128_VIF_BUF1_PITCH_SEL          0x00000001L
#       define  R128_VIF_BUF1_TILE_ADRS          0x00000002L
#       define  R128_VIF_BUF1_BASE_ADRS_MASK     0x03fffff0L
#       define  R128_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF2_BASE_ADRS       0x0448
#       define  R128_VIF_BUF2_PITCH_SEL          0x00000001L
#       define  R128_VIF_BUF2_TILE_ADRS          0x00000002L
#       define  R128_VIF_BUF2_BASE_ADRS_MASK     0x03fffff0L
#       define  R128_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF3_BASE_ADRS       0x044C
#define R128_OV0_VID_BUF4_BASE_ADRS       0x0450
#define R128_OV0_VID_BUF5_BASE_ADRS       0x0454
#define R128_OV0_VID_BUF_PITCH0_VALUE     0x0460
#define R128_OV0_VID_BUF_PITCH1_VALUE     0x0464
#define R128_OV0_AUTO_FLIP_CNTL           0x0470
#define R128_OV0_DEINTERLACE_PATTERN      0x0474
#define R128_OV0_H_INC                    0x0480
#define R128_OV0_STEP_BY                  0x0484
#define R128_OV0_P1_H_ACCUM_INIT          0x0488
#define R128_OV0_P23_H_ACCUM_INIT         0x048C
#define R128_OV0_P1_X_START_END           0x0494
#define R128_OV0_P2_X_START_END           0x0498
#define R128_OV0_P3_X_START_END           0x049C
#define R128_OV0_FILTER_CNTL              0x04A0
#define R128_OV0_FOUR_TAP_COEF_0          0x04B0
#define R128_OV0_FOUR_TAP_COEF_1          0x04B4
#define R128_OV0_FOUR_TAP_COEF_2          0x04B8
#define R128_OV0_FOUR_TAP_COEF_3          0x04BC
#define R128_OV0_FOUR_TAP_COEF_4          0x04C0
#define R128_OV0_COLOUR_CNTL              0x04E0
#define R128_OV0_VIDEO_KEY_CLR            0x04E4
#define R128_OV0_VIDEO_KEY_MSK            0x04E8
#define R128_OV0_GRAPHICS_KEY_CLR         0x04EC
#define R128_OV0_GRAPHICS_KEY_MSK         0x04F0
#define R128_OV0_KEY_CNTL                 0x04F4
#       define  R128_VIDEO_KEY_FN_MASK           0x00000007L
#       define  R128_VIDEO_KEY_FN_FALSE          0x00000000L
#       define  R128_VIDEO_KEY_FN_TRUE           0x00000001L
#       define  R128_VIDEO_KEY_FN_EQ             0x00000004L
#       define  R128_VIDEO_KEY_FN_NE             0x00000005L
#       define  R128_GRAPHIC_KEY_FN_MASK         0x00000070L
#       define  R128_GRAPHIC_KEY_FN_FALSE        0x00000000L
#       define  R128_GRAPHIC_KEY_FN_TRUE         0x00000010L
#       define  R128_GRAPHIC_KEY_FN_EQ           0x00000040L
#       define  R128_GRAPHIC_KEY_FN_NE           0x00000050L
#       define  R128_CMP_MIX_MASK                0x00000100L
#       define  R128_CMP_MIX_OR                  0x00000000L
#       define  R128_CMP_MIX_AND                 0x00000100L
#define R128_OV0_TEST                     0x04F8


#define R128_PALETTE_DATA                 0x00b4