radeon_egl.c

Mesa is an open-source implementation of the OpenGL specification - a system for rendering interacti

   pRADEONDRI->gartTexHandle      = info->gartTexHandle;
   pRADEONDRI->gartTexMapSize     = info->gartTexMapSize;
   pRADEONDRI->log2GARTTexGran    = info->log2GARTTexGran;
   pRADEONDRI->gartTexOffset      = info->gartTexStart;
   pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t);

   /* Don't release the lock now - let the VT switch handler do it. */

   return 1;
}


/**
 * \brief Get Radeon chip family from chipset number.
 *
 * \param info driver private data.
 *
 * \return non-zero on success, or zero on failure.
 *
 * Called by radeonInitFBDev() to set RADEONInfoRec::ChipFamily
 * according to the value of RADEONInfoRec::Chipset.  Fails if the
 * chipset is unrecognized or not appropriate for this driver (i.e., not
 * an r100 style radeon)
 */
static int get_chipfamily_from_chipset( RADEONInfoPtr info )
{
    switch (info->Chipset) {
    case PCI_CHIP_RADEON_LY:
    case PCI_CHIP_RADEON_LZ:
        info->ChipFamily = CHIP_FAMILY_M6;
        break;

    case PCI_CHIP_RADEON_QY:
    case PCI_CHIP_RADEON_QZ:
        info->ChipFamily = CHIP_FAMILY_VE;
        break;

    case PCI_CHIP_R200_QL:
    case PCI_CHIP_R200_QN:
    case PCI_CHIP_R200_QO:
    case PCI_CHIP_R200_Ql:
    case PCI_CHIP_R200_BB:
        info->ChipFamily = CHIP_FAMILY_R200;
        break;

    case PCI_CHIP_RV200_QW: /* RV200 desktop */
    case PCI_CHIP_RV200_QX:
        info->ChipFamily = CHIP_FAMILY_RV200;
        break;

    case PCI_CHIP_RADEON_LW:
    case PCI_CHIP_RADEON_LX:
        info->ChipFamily = CHIP_FAMILY_M7;
        break;

    case PCI_CHIP_RV250_Id:
    case PCI_CHIP_RV250_Ie:
    case PCI_CHIP_RV250_If:
    case PCI_CHIP_RV250_Ig:
        info->ChipFamily = CHIP_FAMILY_RV250;
        break;

    case PCI_CHIP_RV250_Ld:
    case PCI_CHIP_RV250_Le:
    case PCI_CHIP_RV250_Lf:
    case PCI_CHIP_RV250_Lg:
        info->ChipFamily = CHIP_FAMILY_M9;
        break;

    case PCI_CHIP_RV280_Y_:
    case PCI_CHIP_RV280_Ya:
    case PCI_CHIP_RV280_Yb:
    case PCI_CHIP_RV280_Yc:
        info->ChipFamily = CHIP_FAMILY_RV280;
        break;

    case PCI_CHIP_R300_ND:
    case PCI_CHIP_R300_NE:
    case PCI_CHIP_R300_NF:
    case PCI_CHIP_R300_NG:
        info->ChipFamily = CHIP_FAMILY_R300;
        break;

    case PCI_CHIP_RV370_5460:
        info->ChipFamily = CHIP_FAMILY_RV380;
	break;

    default:
        /* Original Radeon/7200 */
        info->ChipFamily = CHIP_FAMILY_RADEON;
    }

    return 1;
}


/**
 * \brief Initialize the framebuffer device mode
 *
 * \param disp display handle.
 *
 * \return one on success, or zero on failure.
 *
 * Fills in \p info with some default values and some information from \p disp
 * and then calls RADEONScreenInit() for the screen initialization.
 *
 * Before exiting clears the framebuffer memory accessing it directly.
 */
static int radeonInitFBDev( driDisplay *disp, RADEONDRIPtr pRADEONDRI )
{
   int err;
   RADEONInfoPtr info = calloc(1, sizeof(*info));

   disp->driverPrivate = (void *)info;

   info->gartFastWrite  = RADEON_DEFAULT_AGP_FAST_WRITE;
   info->gartSize       = RADEON_DEFAULT_AGP_SIZE;
   info->gartTexSize    = RADEON_DEFAULT_AGP_TEX_SIZE;
   info->bufSize       = RADEON_DEFAULT_BUFFER_SIZE;
   info->ringSize      = RADEON_DEFAULT_RING_SIZE;
   info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP;

   fprintf(stderr,
           "Using %d MB AGP aperture\n", info->gartSize);
   fprintf(stderr,
           "Using %d MB for the ring buffer\n", info->ringSize);
   fprintf(stderr,
           "Using %d MB for vertex/indirect buffers\n", info->bufSize);
   fprintf(stderr,
           "Using %d MB for AGP textures\n", info->gartTexSize);
   fprintf(stderr,
           "page flipping %sabled\n", info->page_flip_enable?"en":"dis");

   info->Chipset = disp->chipset;

   if (!get_chipfamily_from_chipset( info )) {
      fprintf(stderr, "Unknown or non-radeon chipset -- cannot continue\n");
      fprintf(stderr, "==> Verify PCI BusID is correct in miniglx.conf\n");
      return 0;
   }
#if 0
   if (info->ChipFamily >= CHIP_FAMILY_R300) {
      fprintf(stderr,
              "Direct rendering not yet supported on "
              "Radeon 9700 and newer cards\n");
      return 0;
   }
#endif

#if 00
   /* don't seem to need this here */
   info->frontPitch = disp->virtualWidth;
#endif

   /* Check the radeon DRM version */
   if (!RADEONCheckDRMVersion(disp, info)) {
      return 0;
   }

   if (RADEONGetCardType(disp, info)<0)
      return 0;

   if (disp->card_type!=RADEON_CARD_AGP) {
      /* Initialize PCI */
      if (!RADEONDRIPciInit(disp, info))
         return 0;
   }
   else {
      /* Initialize AGP */
      if (!RADEONDRIAgpInit(disp, info))
         return 0;
   }

   if (!RADEONScreenInit( disp, info, pRADEONDRI))
      return 0;

   /* Initialize and start the CP if required */
   if ((err = drmCommandNone(disp->drmFD, DRM_RADEON_CP_START)) != 0) {
      fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err);
      return 0;
   }

   return 1;
}


/**
 * Create list of all supported surface configs, attach list to the display.
 */
static EGLBoolean
radeonFillInConfigs(_EGLDisplay *disp, unsigned pixel_bits,
                    unsigned depth_bits,
                    unsigned stencil_bits, GLboolean have_back_buffer)
{
   _EGLConfig *configs;
   _EGLConfig *c;
   unsigned int i, num_configs;
   unsigned int depth_buffer_factor;
   unsigned int back_buffer_factor;
   GLenum fb_format;
   GLenum fb_type;

   /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
   * enough to add support.  Basically, if a context is created with an
   * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
   * will never be used.
   */
   static const GLenum back_buffer_modes[] = {
            GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
         };

   u_int8_t depth_bits_array[2];
   u_int8_t stencil_bits_array[2];

   depth_bits_array[0] = depth_bits;
   depth_bits_array[1] = depth_bits;

   /* Just like with the accumulation buffer, always provide some modes
   * with a stencil buffer.  It will be a sw fallback, but some apps won't
   * care about that.
   */
   stencil_bits_array[0] = 0;
   stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;

   depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
   back_buffer_factor = (have_back_buffer) ? 2 : 1;

   num_configs = depth_buffer_factor * back_buffer_factor * 2;

   if (pixel_bits == 16) {
      fb_format = GL_RGB;
      fb_type = GL_UNSIGNED_SHORT_5_6_5;
   } else {
      fb_format = GL_RGBA;
      fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
   }

   configs = calloc(sizeof(*configs), num_configs);
   c = configs;
   if (!_eglFillInConfigs(c, fb_format, fb_type,
                          depth_bits_array, stencil_bits_array,
                          depth_buffer_factor,
                          back_buffer_modes, back_buffer_factor,
                          GLX_TRUE_COLOR)) {
      fprintf(stderr, "[%s:%u] Error creating FBConfig!\n",
               __func__, __LINE__);
      return EGL_FALSE;
   }

   /* Mark the visual as slow if there are "fake" stencil bits.
   */
   for (i = 0, c = configs; i < num_configs; i++, c++) {
      int stencil = GET_CONFIG_ATTRIB(c, EGL_STENCIL_SIZE);
      if ((stencil != 0)  && (stencil != stencil_bits)) {
         SET_CONFIG_ATTRIB(c, EGL_CONFIG_CAVEAT, EGL_SLOW_CONFIG);
      }
   }

   for (i = 0, c = configs; i < num_configs; i++, c++)
      _eglAddConfig(disp, c);

   free(configs);

   return EGL_TRUE;
}


/**
 * Show the given surface on the named screen.
 * If surface is EGL_NO_SURFACE, disable the screen's output.
 */
static EGLBoolean
radeonShowScreenSurfaceMESA(_EGLDriver *drv, EGLDisplay dpy, EGLScreenMESA screen,
                      EGLSurface surface, EGLModeMESA m)
{
   EGLBoolean b = _eglDRIShowScreenSurfaceMESA(drv, dpy, screen, surface, m);
   return b;
}


/**
 * Called via eglInitialize() by user.
 */
static EGLBoolean
radeonInitialize(_EGLDriver *drv, EGLDisplay dpy, EGLint *major, EGLint *minor)
{
   __DRIframebuffer framebuffer;
   driDisplay *display;

   /* one-time init */
   radeon_drm_page_size = getpagesize();

   if (!_eglDRIInitialize(drv, dpy, major, minor))
      return EGL_FALSE;

   display = Lookup_driDisplay(dpy);

   framebuffer.dev_priv_size = sizeof(RADEONDRIRec);
   framebuffer.dev_priv = malloc(sizeof(RADEONDRIRec));

   /* XXX we shouldn't hard-code values here! */
   /* we won't know the screen surface size until the user calls
    * eglCreateScreenSurfaceMESA().
    */
#if 0
   display->virtualWidth = 1024;
   display->virtualHeight = 768;
#else
   display->virtualWidth = 1280;
   display->virtualHeight = 1024;
#endif
   display->bpp = 32;
   display->cpp = 4;

   if (!_eglDRIGetDisplayInfo(display))
      return EGL_FALSE;

   framebuffer.base = display->pFB;
   framebuffer.width = display->virtualWidth;
   framebuffer.height = display->virtualHeight;
   framebuffer.stride = display->virtualWidth;
   framebuffer.size = display->fbSize;
   radeonInitFBDev( display, framebuffer.dev_priv );

   if (!_eglDRICreateDisplay(display, &framebuffer))
      return EGL_FALSE;

   if (!_eglDRICreateScreens(display))
      return EGL_FALSE;

   /* create a variety of both 32 and 16-bit configurations */
   radeonFillInConfigs(&display->Base, 32, 24, 8, GL_TRUE);
   radeonFillInConfigs(&display->Base, 16, 16, 0, GL_TRUE);

   drv->Initialized = EGL_TRUE;
   return EGL_TRUE;
}


/**
 * The bootstrap function.  Return a new radeonDriver object and
 * plug in API functions.
 */
_EGLDriver *
_eglMain(_EGLDisplay *dpy)
{
   radeonDriver *radeon;

   radeon = (radeonDriver *) calloc(1, sizeof(*radeon));
   if (!radeon) {
      return NULL;
   }

   /* First fill in the dispatch table with defaults */
   _eglDRIInitDriverFallbacks(&radeon->Base);

   /* then plug in our radeon-specific functions */
   radeon->Base.API.Initialize = radeonInitialize;
   radeon->Base.API.ShowScreenSurfaceMESA = radeonShowScreenSurfaceMESA;

   return &radeon->Base;
}