📄 radeon_maos_arrays.c
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radeonAllocDmaRegion( rmesa, rvb, size * 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = size; } else { radeonAllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = size; rvb->aos_size = size; } /* Emit the data */ switch (size) { case 1: emit_vec4( ctx, rvb, data, stride, count ); break; case 2: emit_vec8( ctx, rvb, data, stride, count ); break; case 3: emit_vec12( ctx, rvb, data, stride, count ); break; case 4: emit_vec16( ctx, rvb, data, stride, count ); break; default: assert(0); exit(1); break; }}static void emit_s0_vec( GLcontext *ctx, struct radeon_dma_region *rvb, char *data, int stride, int count ){ int i; int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s count %d stride %d\n", __FUNCTION__, count, stride); for (i = 0; i < count; i++) { out[0] = *(int *)data; out[1] = 0; out += 2; data += stride; }}static void emit_stq_vec( GLcontext *ctx, struct radeon_dma_region *rvb, char *data, int stride, int count ){ int i; int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s count %d stride %d\n", __FUNCTION__, count, stride); for (i = 0; i < count; i++) { out[0] = *(int *)data; out[1] = *(int *)(data+4); out[2] = *(int *)(data+12); out += 3; data += stride; }}static void emit_tex_vector( GLcontext *ctx, struct radeon_dma_region *rvb, char *data, int size, int stride, int count ){ radeonContextPtr rmesa = RADEON_CONTEXT(ctx); int emitsize; if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s %d/%d\n", __FUNCTION__, count, size); assert (!rvb->buf); switch (size) { case 4: emitsize = 3; break; case 3: emitsize = 3; break; default: emitsize = 2; break; } if (stride == 0) { radeonAllocDmaRegion( rmesa, rvb, 4 * emitsize, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = emitsize; } else { radeonAllocDmaRegion( rmesa, rvb, 4 * emitsize * count, 4 ); rvb->aos_start = GET_START(rvb); rvb->aos_stride = emitsize; rvb->aos_size = emitsize; } /* Emit the data */ switch (size) { case 1: emit_s0_vec( ctx, rvb, data, stride, count ); break; case 2: emit_vec8( ctx, rvb, data, stride, count ); break; case 3: emit_vec12( ctx, rvb, data, stride, count ); break; case 4: emit_stq_vec( ctx, rvb, data, stride, count ); break; default: assert(0); exit(1); break; }}/* Emit any changed arrays to new GART memory, re-emit a packet to * update the arrays. */void radeonEmitArrays( GLcontext *ctx, GLuint inputs ){ radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb; struct radeon_dma_region **component = rmesa->tcl.aos_components; GLuint nr = 0; GLuint vfmt = 0; GLuint count = VB->Count; GLuint vtx, unit; #if 0 if (RADEON_DEBUG & DEBUG_VERTS) _tnl_print_vert_flags( __FUNCTION__, inputs );#endif if (1) { if (!rmesa->tcl.obj.buf) emit_vector( ctx, &rmesa->tcl.obj, (char *)VB->ObjPtr->data, VB->ObjPtr->size, VB->ObjPtr->stride, count); switch( VB->ObjPtr->size ) { case 4: vfmt |= RADEON_CP_VC_FRMT_W0; case 3: vfmt |= RADEON_CP_VC_FRMT_Z; case 2: vfmt |= RADEON_CP_VC_FRMT_XY; default: break; } component[nr++] = &rmesa->tcl.obj; } if (inputs & VERT_BIT_NORMAL) { if (!rmesa->tcl.norm.buf) emit_vector( ctx, &(rmesa->tcl.norm), (char *)VB->NormalPtr->data, 3, VB->NormalPtr->stride, count); vfmt |= RADEON_CP_VC_FRMT_N0; component[nr++] = &rmesa->tcl.norm; } if (inputs & VERT_BIT_COLOR0) { int emitsize; if (VB->ColorPtr[0]->size == 4 && (VB->ColorPtr[0]->stride != 0 || VB->ColorPtr[0]->data[0][3] != 1.0)) { vfmt |= RADEON_CP_VC_FRMT_FPCOLOR | RADEON_CP_VC_FRMT_FPALPHA; emitsize = 4; } else { vfmt |= RADEON_CP_VC_FRMT_FPCOLOR; emitsize = 3; } if (!rmesa->tcl.rgba.buf) emit_vector( ctx, &(rmesa->tcl.rgba), (char *)VB->ColorPtr[0]->data, emitsize, VB->ColorPtr[0]->stride, count); component[nr++] = &rmesa->tcl.rgba; } if (inputs & VERT_BIT_COLOR1) { if (!rmesa->tcl.spec.buf) { emit_vector( ctx, &rmesa->tcl.spec, (char *)VB->SecondaryColorPtr[0]->data, 3, VB->SecondaryColorPtr[0]->stride, count); } vfmt |= RADEON_CP_VC_FRMT_FPSPEC; component[nr++] = &rmesa->tcl.spec; }/* FIXME: not sure if this is correct. May need to stitch this together with secondary color. It seems odd that for primary color color and alpha values are emitted together but for secondary color not. */ if (inputs & VERT_BIT_FOG) { if (!rmesa->tcl.fog.buf) emit_vecfog( ctx, &(rmesa->tcl.fog), (char *)VB->FogCoordPtr->data, VB->FogCoordPtr->stride, count); vfmt |= RADEON_CP_VC_FRMT_FPFOG; component[nr++] = &rmesa->tcl.fog; } vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1|RADEON_TCL_VTX_Q2)); for (unit = 0; unit < ctx->Const.MaxTextureUnits; unit++) { if (inputs & VERT_BIT_TEX(unit)) { if (!rmesa->tcl.tex[unit].buf) emit_tex_vector( ctx, &(rmesa->tcl.tex[unit]), (char *)VB->TexCoordPtr[unit]->data, VB->TexCoordPtr[unit]->size, VB->TexCoordPtr[unit]->stride, count ); vfmt |= RADEON_ST_BIT(unit); /* assume we need the 3rd coord if texgen is active for r/q OR at least 3 coords are submitted. This may not be 100% correct */ if (VB->TexCoordPtr[unit]->size >= 3) { vtx |= RADEON_Q_BIT(unit); vfmt |= RADEON_Q_BIT(unit); } if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) vtx |= RADEON_Q_BIT(unit); else if ((VB->TexCoordPtr[unit]->size >= 3) && ((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) { GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3); if (((rmesa->NeedTexMatrix >> unit) & 1) && (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; } component[nr++] = &rmesa->tcl.tex[unit]; } } if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) { RADEON_STATECHANGE( rmesa, tcl ); rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx; } rmesa->tcl.nr_aos_components = nr; rmesa->tcl.vertex_format = vfmt;}void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ){ radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); GLuint unit;#if 0 if (RADEON_DEBUG & DEBUG_VERTS) _tnl_print_vert_flags( __FUNCTION__, newinputs );#endif if (newinputs & VERT_BIT_POS) radeonReleaseDmaRegion( rmesa, &rmesa->tcl.obj, __FUNCTION__ ); if (newinputs & VERT_BIT_NORMAL) radeonReleaseDmaRegion( rmesa, &rmesa->tcl.norm, __FUNCTION__ ); if (newinputs & VERT_BIT_COLOR0) radeonReleaseDmaRegion( rmesa, &rmesa->tcl.rgba, __FUNCTION__ ); if (newinputs & VERT_BIT_COLOR1) radeonReleaseDmaRegion( rmesa, &rmesa->tcl.spec, __FUNCTION__ ); if (newinputs & VERT_BIT_FOG) radeonReleaseDmaRegion( rmesa, &rmesa->tcl.fog, __FUNCTION__ ); for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { if (newinputs & VERT_BIT_TEX(unit)) radeonReleaseDmaRegion( rmesa, &rmesa->tcl.tex[unit], __FUNCTION__ ); }}
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