📄 radeon_tex.c
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/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c,v 1.6 2002/09/16 18:05:20 eich Exp $ *//*Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and VA Linux Systems Inc., Fremont, California.All Rights Reserved.Permission is hereby granted, free of charge, to any person obtaininga copy of this software and associated documentation files (the"Software"), to deal in the Software without restriction, includingwithout limitation the rights to use, copy, modify, merge, publish,distribute, sublicense, and/or sell copies of the Software, and topermit persons to whom the Software is furnished to do so, subject tothe following conditions:The above copyright notice and this permission notice (including thenext paragraph) shall be included in all copies or substantialportions of the Software.THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OFMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BELIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTIONOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTIONWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.*//* * Authors: * Gareth Hughes <gareth@valinux.com> * Brian Paul <brianp@valinux.com> */#include "glheader.h"#include "imports.h"#include "colormac.h"#include "context.h"#include "enums.h"#include "image.h"#include "simple_list.h"#include "texformat.h"#include "texstore.h"#include "teximage.h"#include "texobj.h"#include "radeon_context.h"#include "radeon_state.h"#include "radeon_ioctl.h"#include "radeon_swtcl.h"#include "radeon_tex.h"#include "xmlpool.h"/** * Set the texture wrap modes. * * \param t Texture object whose wrap modes are to be set * \param swrap Wrap mode for the \a s texture coordinate * \param twrap Wrap mode for the \a t texture coordinate */static void radeonSetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap ){ GLboolean is_clamp = GL_FALSE; GLboolean is_clamp_to_border = GL_FALSE; t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK | RADEON_BORDER_MODE_D3D); switch ( swrap ) { case GL_REPEAT: t->pp_txfilter |= RADEON_CLAMP_S_WRAP; break; case GL_CLAMP: t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL; is_clamp = GL_TRUE; break; case GL_CLAMP_TO_EDGE: t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST; break; case GL_CLAMP_TO_BORDER: t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL; is_clamp_to_border = GL_TRUE; break; case GL_MIRRORED_REPEAT: t->pp_txfilter |= RADEON_CLAMP_S_MIRROR; break; case GL_MIRROR_CLAMP_EXT: t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL; is_clamp = GL_TRUE; break; case GL_MIRROR_CLAMP_TO_EDGE_EXT: t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST; break; case GL_MIRROR_CLAMP_TO_BORDER_EXT: t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL; is_clamp_to_border = GL_TRUE; break; default: _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__); } switch ( twrap ) { case GL_REPEAT: t->pp_txfilter |= RADEON_CLAMP_T_WRAP; break; case GL_CLAMP: t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL; is_clamp = GL_TRUE; break; case GL_CLAMP_TO_EDGE: t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_LAST; break; case GL_CLAMP_TO_BORDER: t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL; is_clamp_to_border = GL_TRUE; break; case GL_MIRRORED_REPEAT: t->pp_txfilter |= RADEON_CLAMP_T_MIRROR; break; case GL_MIRROR_CLAMP_EXT: t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL; is_clamp = GL_TRUE; break; case GL_MIRROR_CLAMP_TO_EDGE_EXT: t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_LAST; break; case GL_MIRROR_CLAMP_TO_BORDER_EXT: t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL; is_clamp_to_border = GL_TRUE; break; default: _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__); } if ( is_clamp_to_border ) { t->pp_txfilter |= RADEON_BORDER_MODE_D3D; } t->border_fallback = (is_clamp && is_clamp_to_border);}static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max ){ t->pp_txfilter &= ~RADEON_MAX_ANISO_MASK; if ( max == 1.0 ) { t->pp_txfilter |= RADEON_MAX_ANISO_1_TO_1; } else if ( max <= 2.0 ) { t->pp_txfilter |= RADEON_MAX_ANISO_2_TO_1; } else if ( max <= 4.0 ) { t->pp_txfilter |= RADEON_MAX_ANISO_4_TO_1; } else if ( max <= 8.0 ) { t->pp_txfilter |= RADEON_MAX_ANISO_8_TO_1; } else { t->pp_txfilter |= RADEON_MAX_ANISO_16_TO_1; }}/** * Set the texture magnification and minification modes. * * \param t Texture whose filter modes are to be set * \param minf Texture minification mode * \param magf Texture magnification mode */static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf ){ GLuint anisotropy = (t->pp_txfilter & RADEON_MAX_ANISO_MASK); t->pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK); /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */ if ( t->base.tObj->Target == GL_TEXTURE_CUBE_MAP ) { switch ( minf ) { case GL_NEAREST: case GL_NEAREST_MIPMAP_NEAREST: case GL_NEAREST_MIPMAP_LINEAR: t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST; break; case GL_LINEAR: case GL_LINEAR_MIPMAP_NEAREST: case GL_LINEAR_MIPMAP_LINEAR: t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR; break; default: break; } } else if ( anisotropy == RADEON_MAX_ANISO_1_TO_1 ) { switch ( minf ) { case GL_NEAREST: t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST; break; case GL_LINEAR: t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR; break; case GL_NEAREST_MIPMAP_NEAREST: t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST; break; case GL_NEAREST_MIPMAP_LINEAR: t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST; break; case GL_LINEAR_MIPMAP_NEAREST: t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR; break; case GL_LINEAR_MIPMAP_LINEAR: t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR; break; } } else { switch ( minf ) { case GL_NEAREST: t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST; break; case GL_LINEAR: t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_LINEAR; break; case GL_NEAREST_MIPMAP_NEAREST: case GL_LINEAR_MIPMAP_NEAREST: t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST; break; case GL_NEAREST_MIPMAP_LINEAR: case GL_LINEAR_MIPMAP_LINEAR: t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR; break; } } switch ( magf ) { case GL_NEAREST: t->pp_txfilter |= RADEON_MAG_FILTER_NEAREST; break; case GL_LINEAR: t->pp_txfilter |= RADEON_MAG_FILTER_LINEAR; break; }}static void radeonSetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] ){ t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] );}/** * Allocate space for and load the mesa images into the texture memory block. * This will happen before drawing with a new texture, or drawing with a * texture after it was swapped out or teximaged again. */static radeonTexObjPtr radeonAllocTexObj( struct gl_texture_object *texObj ){ radeonTexObjPtr t; t = CALLOC_STRUCT( radeon_tex_obj ); texObj->DriverData = t; if ( t != NULL ) { if ( RADEON_DEBUG & DEBUG_TEXTURE ) { fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)texObj, (void *)t ); } /* Initialize non-image-dependent parts of the state: */ t->base.tObj = texObj; t->border_fallback = GL_FALSE; t->pp_txfilter = RADEON_BORDER_MODE_OGL; t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP | RADEON_TXFORMAT_PERSPECTIVE_ENABLE); make_empty_list( & t->base ); radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT ); radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy ); radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter ); radeonSetTexBorderColor( t, texObj->_BorderChan ); } return t;}static const struct gl_texture_format *radeonChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ){ radeonContextPtr rmesa = RADEON_CONTEXT(ctx); const GLboolean do32bpt = ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32 ); const GLboolean force16bpt = ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 ); (void) format; switch ( internalFormat ) { case 4: case GL_RGBA: case GL_COMPRESSED_RGBA: switch ( type ) { case GL_UNSIGNED_INT_10_10_10_2: case GL_UNSIGNED_INT_2_10_10_10_REV: return do32bpt ? _dri_texformat_argb8888 : _dri_texformat_argb1555; case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: return _dri_texformat_argb4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: return _dri_texformat_argb1555; default: return do32bpt ? _dri_texformat_argb8888 : _dri_texformat_argb4444; } case 3: case GL_RGB: case GL_COMPRESSED_RGB: switch ( type ) { case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: return _dri_texformat_argb4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: return _dri_texformat_argb1555; case GL_UNSIGNED_SHORT_5_6_5: case GL_UNSIGNED_SHORT_5_6_5_REV: return _dri_texformat_rgb565; default: return do32bpt ? _dri_texformat_argb8888 : _dri_texformat_rgb565; } case GL_RGBA8: case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: return !force16bpt ? _dri_texformat_argb8888 : _dri_texformat_argb4444; case GL_RGBA4: case GL_RGBA2: return _dri_texformat_argb4444; case GL_RGB5_A1: return _dri_texformat_argb1555; case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: return !force16bpt ? _dri_texformat_argb8888 : _dri_texformat_rgb565; case GL_RGB5: case GL_RGB4: case GL_R3_G3_B2: return _dri_texformat_rgb565; case GL_ALPHA: case GL_ALPHA4: case GL_ALPHA8: case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: return _dri_texformat_a8; case 1: case GL_LUMINANCE: case GL_LUMINANCE4: case GL_LUMINANCE8: case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: return _dri_texformat_l8; case 2: case GL_LUMINANCE_ALPHA: case GL_LUMINANCE4_ALPHA4: case GL_LUMINANCE6_ALPHA2: case GL_LUMINANCE8_ALPHA8: case GL_LUMINANCE12_ALPHA4: case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: return _dri_texformat_al88; case GL_INTENSITY: case GL_INTENSITY4: case GL_INTENSITY8: case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: return _dri_texformat_i8; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) return &_mesa_texformat_ycbcr; else return &_mesa_texformat_ycbcr_rev; case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: return &_mesa_texformat_rgb_dxt1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: return &_mesa_texformat_rgba_dxt1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: return &_mesa_texformat_rgba_dxt3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: return &_mesa_texformat_rgba_dxt5; default: _mesa_problem(ctx, "unexpected texture format in %s", __FUNCTION__); return NULL; } return NULL; /* never get here */}static void radeonTexImage1D( GLcontext *ctx, GLenum target, GLint level, GLint internalFormat, GLint width, GLint border, GLenum format, GLenum type, const GLvoid *pixels, const struct gl_pixelstore_attrib *packing, struct gl_texture_object *texObj, struct gl_texture_image *texImage ){ driTextureObject * t = (driTextureObject *) texObj->DriverData; if ( t ) { driSwapOutTextureObject( t ); } else { t = (driTextureObject *) radeonAllocTexObj( texObj ); if (!t) {
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