radeon_context.h

Mesa is an open-source implementation of the OpenGL specification - a system for rendering interacti

 */
#define UCP_CMD_0      0
#define UCP_X          1
#define UCP_Y          2
#define UCP_Z          3
#define UCP_W          4
#define UCP_STATE_SIZE 5

/* GLT - Global ambient
 */
#define GLT_CMD_0      0
#define GLT_RED        1
#define GLT_GREEN      2
#define GLT_BLUE       3
#define GLT_ALPHA      4
#define GLT_STATE_SIZE 5

/* EYE
 */
#define EYE_CMD_0          0
#define EYE_X              1
#define EYE_Y              2
#define EYE_Z              3
#define EYE_RESCALE_FACTOR 4
#define EYE_STATE_SIZE     5

#define SHN_CMD_0          0
#define SHN_SHININESS      1
#define SHN_STATE_SIZE     2

struct radeon_hw_state {
	/* Head of the linked list of state atoms. */
	struct radeon_state_atom atomlist;

	/* Hardware state, stored as cmdbuf commands:  
	 *   -- Need to doublebuffer for
	 *           - eliding noop statechange loops? (except line stipple count)
	 */
	struct radeon_state_atom ctx;
	struct radeon_state_atom set;
	struct radeon_state_atom lin;
	struct radeon_state_atom msk;
	struct radeon_state_atom vpt;
	struct radeon_state_atom tcl;
	struct radeon_state_atom msc;
	struct radeon_state_atom tex[3];
	struct radeon_state_atom cube[3];
	struct radeon_state_atom zbs;
	struct radeon_state_atom mtl;
	struct radeon_state_atom mat[6];
	struct radeon_state_atom lit[8];	/* includes vec, scl commands */
	struct radeon_state_atom ucp[6];
	struct radeon_state_atom eye;	/* eye pos */
	struct radeon_state_atom grd;	/* guard band clipping */
	struct radeon_state_atom fog;
	struct radeon_state_atom glt;
	struct radeon_state_atom txr[3];	/* for NPOT */

	int max_state_size;	/* Number of bytes necessary for a full state emit. */
	GLboolean is_dirty, all_dirty;
};

struct radeon_state {
	/* Derived state for internal purposes:
	 */
	struct radeon_colorbuffer_state color;
	struct radeon_depthbuffer_state depth;
	struct radeon_scissor_state scissor;
	struct radeon_stencilbuffer_state stencil;
	struct radeon_stipple_state stipple;
	struct radeon_texture_state texture;
};

/* Need refcounting on dma buffers:
 */
struct radeon_dma_buffer {
	int refcount;		/* the number of retained regions in buf */
	drmBufPtr buf;
};

#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset +			\
			(rvb)->address - rmesa->dma.buf0_address +	\
			(rvb)->start)

/* A retained region, eg vertices for indexed vertices.
 */
struct radeon_dma_region {
	struct radeon_dma_buffer *buf;
	char *address;		/* == buf->address */
	int start, end, ptr;	/* offsets from start of buf */
	int aos_start;
	int aos_stride;
	int aos_size;
};

struct radeon_dma {
	/* Active dma region.  Allocations for vertices and retained
	 * regions come from here.  Also used for emitting random vertices,
	 * these may be flushed by calling flush_current();
	 */
	struct radeon_dma_region current;

	void (*flush) (radeonContextPtr);

	char *buf0_address;	/* start of buf[0], for index calcs */
	GLuint nr_released_bufs;	/* flush after so many buffers released */
};

struct radeon_dri_mirror {
	__DRIcontextPrivate *context;	/* DRI context */
	__DRIscreenPrivate *screen;	/* DRI screen */

   /**
    * DRI drawable bound to this context for drawing.
    */
	__DRIdrawablePrivate *drawable;

   /**
    * DRI drawable bound to this context for reading.
    */
	__DRIdrawablePrivate *readable;

	drm_context_t hwContext;
	drm_hw_lock_t *hwLock;
	int fd;
	int drmMinor;
};

#define RADEON_CMD_BUF_SZ  (8*1024)

struct radeon_store {
	GLuint statenr;
	GLuint primnr;
	char cmd_buf[RADEON_CMD_BUF_SZ];
	int cmd_used;
	int elts_start;
};

/* radeon_tcl.c
 */
struct radeon_tcl_info {
	GLuint vertex_format;
	GLuint hw_primitive;

	/* Temporary for cases where incoming vertex data is incompatible
	 * with maos code.
	 */
	GLvector4f ObjClean;

	struct radeon_dma_region *aos_components[8];
	GLuint nr_aos_components;

	GLuint *Elts;

	struct radeon_dma_region indexed_verts;
	struct radeon_dma_region obj;
	struct radeon_dma_region rgba;
	struct radeon_dma_region spec;
	struct radeon_dma_region fog;
	struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS];
	struct radeon_dma_region norm;
};

/* radeon_swtcl.c
 */
struct radeon_swtcl_info {
	GLuint RenderIndex;
	GLuint vertex_size;
	GLuint vertex_format;

	struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
	GLuint vertex_attr_count;

	GLubyte *verts;

	/* Fallback rasterization functions
	 */
	radeon_point_func draw_point;
	radeon_line_func draw_line;
	radeon_tri_func draw_tri;

	GLuint hw_primitive;
	GLenum render_primitive;
	GLuint numverts;

   /**
    * Offset of the 4UB color data within a hardware (swtcl) vertex.
    */
	GLuint coloroffset;

   /**
    * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
    */
	GLuint specoffset;

	GLboolean needproj;

	struct radeon_dma_region indexed_verts;
};

struct radeon_ioctl {
	GLuint vertex_offset;
	GLuint vertex_size;
};

#define RADEON_MAX_PRIMS 64

struct radeon_prim {
	GLuint start;
	GLuint end;
	GLuint prim;
};

/* A maximum total of 20 elements per vertex:  3 floats for position, 3
 * floats for normal, 4 floats for color, 4 bytes for secondary color,
 * 3 floats for each texture unit (9 floats total).
 * 
 * The position data is never actually stored here, so 3 elements could be
 * trimmed out of the buffer. This number is only valid for vtxfmt!
 */
#define RADEON_MAX_VERTEX_SIZE 20

struct radeon_context {
	GLcontext *glCtx;	/* Mesa context */

	/* Driver and hardware state management
	 */
	struct radeon_hw_state hw;
	struct radeon_state state;

	/* Texture object bookkeeping
	 */
	unsigned nr_heaps;
	driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
	driTextureObject swapped;
	int texture_depth;
	float initialMaxAnisotropy;

	/* Rasterization and vertex state:
	 */
	GLuint TclFallback;
	GLuint Fallback;
	GLuint NewGLState;
	 DECLARE_RENDERINPUTS(tnl_index_bitset);	/* index of bits for last tnl_install_attrs */

	/* Vertex buffers
	 */
	struct radeon_ioctl ioctl;
	struct radeon_dma dma;
	struct radeon_store store;
	/* A full state emit as of the first state emit in the main store, in case
	 * the context is lost.
	 */
	struct radeon_store backup_store;

	/* Page flipping
	 */
	GLuint doPageFlip;

	/* Busy waiting
	 */
	GLuint do_usleeps;
	GLuint do_irqs;
	GLuint irqsEmitted;
	drm_radeon_irq_wait_t iw;

	/* Drawable, cliprect and scissor information
	 */
	GLuint numClipRects;	/* Cliprects for the draw buffer */
	drm_clip_rect_t *pClipRects;
	unsigned int lastStamp;
	GLboolean lost_context;
	GLboolean save_on_next_emit;
	radeonScreenPtr radeonScreen;	/* Screen private DRI data */
	drm_radeon_sarea_t *sarea;	/* Private SAREA data */

	/* TCL stuff
	 */
	GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS];
	GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS];
	GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS];
	GLuint TexGenEnabled;
	GLuint NeedTexMatrix;
	GLuint TexMatColSwap;
	GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS];
	GLuint last_ReallyEnabled;

	/* VBI
	 */
	int64_t swap_ust;
	int64_t swap_missed_ust;

	GLuint swap_count;
	GLuint swap_missed_count;

	/* radeon_tcl.c
	 */
	struct radeon_tcl_info tcl;

	/* radeon_swtcl.c
	 */
	struct radeon_swtcl_info swtcl;

	/* Mirrors of some DRI state
	 */
	struct radeon_dri_mirror dri;

	/* Configuration cache
	 */
	driOptionCache optionCache;

	GLboolean using_hyperz;
	GLboolean texmicrotile;

	/* Performance counters
	 */
	GLuint boxes;		/* Draw performance boxes */
	GLuint hardwareWentIdle;
	GLuint c_clears;
	GLuint c_drawWaits;
	GLuint c_textureSwaps;
	GLuint c_textureBytes;
	GLuint c_vertexBuffers;
};

#define RADEON_CONTEXT(ctx)		((radeonContextPtr)(ctx->DriverCtx))

static INLINE GLuint radeonPackColor(GLuint cpp,
                                     GLubyte r, GLubyte g,
                                     GLubyte b, GLubyte a)
{
	switch (cpp) {
	case 2:
		return PACK_COLOR_565(r, g, b);
	case 4:
		return PACK_COLOR_8888(a, r, g, b);
	default:
		return 0;
	}
}

#define RADEON_OLD_PACKETS 1

extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
				     __DRIcontextPrivate * driContextPriv,
				     void *sharedContextPrivate);
extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv);
extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
				int x, int y, int w, int h);
extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
				   __DRIdrawablePrivate * driDrawPriv,
				   __DRIdrawablePrivate * driReadPriv);
extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);

/* ================================================================
 * Debugging:
 */
#define DO_DEBUG		1

#if DO_DEBUG
extern int RADEON_DEBUG;
#else
#define RADEON_DEBUG		0
#endif

#define DEBUG_TEXTURE	0x0001
#define DEBUG_STATE	0x0002
#define DEBUG_IOCTL	0x0004
#define DEBUG_PRIMS	0x0008
#define DEBUG_VERTS	0x0010
#define DEBUG_FALLBACKS	0x0020
#define DEBUG_VFMT	0x0040
#define DEBUG_CODEGEN	0x0080
#define DEBUG_VERBOSE	0x0100
#define DEBUG_DRI       0x0200
#define DEBUG_DMA       0x0400
#define DEBUG_SANITY    0x0800
#define DEBUG_SYNC      0x1000

#endif				/* __RADEON_CONTEXT_H__ */