📄 brw_eu.h
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static INLINE struct brw_reg brw_address_reg( GLuint subnr ){ return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr);}/* If/else instructions break in align16 mode if writemask & swizzle * aren't xyzw. This goes against the convention for other scalar * regs: */static INLINE struct brw_reg brw_ip_reg( void ){ return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_IP, 0, BRW_REGISTER_TYPE_UD, BRW_VERTICAL_STRIDE_4, /* ? */ BRW_WIDTH_1, BRW_HORIZONTAL_STRIDE_0, BRW_SWIZZLE_XYZW, /* NOTE! */ WRITEMASK_XYZW); /* NOTE! */}static INLINE struct brw_reg brw_acc_reg( void ){ return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ACCUMULATOR, 0);}static INLINE struct brw_reg brw_flag_reg( void ){ return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_FLAG, 0);}static INLINE struct brw_reg brw_mask_reg( GLuint subnr ){ return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, subnr);}static INLINE struct brw_reg brw_message_reg( GLuint nr ){ return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, nr, 0);}/* This is almost always called with a numeric constant argument, so * make things easy to evaluate at compile time: */static INLINE GLuint cvt( GLuint val ){ switch (val) { case 0: return 0; case 1: return 1; case 2: return 2; case 4: return 3; case 8: return 4; case 16: return 5; case 32: return 6; } return 0;}static INLINE struct brw_reg stride( struct brw_reg reg, GLuint vstride, GLuint width, GLuint hstride ){ reg.vstride = cvt(vstride); reg.width = cvt(width) - 1; reg.hstride = cvt(hstride); return reg;}static INLINE struct brw_reg vec16( struct brw_reg reg ){ return stride(reg, 16,16,1);}static INLINE struct brw_reg vec8( struct brw_reg reg ){ return stride(reg, 8,8,1);}static INLINE struct brw_reg vec4( struct brw_reg reg ){ return stride(reg, 4,4,1);}static INLINE struct brw_reg vec2( struct brw_reg reg ){ return stride(reg, 2,2,1);}static INLINE struct brw_reg vec1( struct brw_reg reg ){ return stride(reg, 0,1,0);}static INLINE struct brw_reg get_element( struct brw_reg reg, GLuint elt ){ return vec1(suboffset(reg, elt));}static INLINE struct brw_reg get_element_ud( struct brw_reg reg, GLuint elt ){ return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));}static INLINE struct brw_reg brw_swizzle( struct brw_reg reg, GLuint x, GLuint y, GLuint z, GLuint w){ reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x), BRW_GET_SWZ(reg.dw1.bits.swizzle, y), BRW_GET_SWZ(reg.dw1.bits.swizzle, z), BRW_GET_SWZ(reg.dw1.bits.swizzle, w)); return reg;}static INLINE struct brw_reg brw_swizzle1( struct brw_reg reg, GLuint x ){ return brw_swizzle(reg, x, x, x, x);}static INLINE struct brw_reg brw_writemask( struct brw_reg reg, GLuint mask ){ reg.dw1.bits.writemask &= mask; return reg;}static INLINE struct brw_reg brw_set_writemask( struct brw_reg reg, GLuint mask ){ reg.dw1.bits.writemask = mask; return reg;}static INLINE struct brw_reg negate( struct brw_reg reg ){ reg.negate ^= 1; return reg;}static INLINE struct brw_reg brw_abs( struct brw_reg reg ){ reg.abs = 1; return reg;}/*********************************************************************** */static INLINE struct brw_reg brw_vec4_indirect( GLuint subnr, GLint offset ){ struct brw_reg reg = brw_vec4_grf(0, 0); reg.subnr = subnr; reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; reg.dw1.bits.indirect_offset = offset; return reg;}static INLINE struct brw_reg brw_vec1_indirect( GLuint subnr, GLint offset ){ struct brw_reg reg = brw_vec1_grf(0, 0); reg.subnr = subnr; reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; reg.dw1.bits.indirect_offset = offset; return reg;}static INLINE struct brw_reg deref_4f(struct brw_indirect ptr, GLint offset){ return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);}static INLINE struct brw_reg deref_1f(struct brw_indirect ptr, GLint offset){ return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);}static INLINE struct brw_reg deref_4b(struct brw_indirect ptr, GLint offset){ return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);}static INLINE struct brw_reg deref_1uw(struct brw_indirect ptr, GLint offset){ return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);}static INLINE struct brw_reg deref_1d(struct brw_indirect ptr, GLint offset){ return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D);}static INLINE struct brw_reg deref_1ud(struct brw_indirect ptr, GLint offset){ return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);}static INLINE struct brw_reg get_addr_reg(struct brw_indirect ptr){ return brw_address_reg(ptr.addr_subnr);}static INLINE struct brw_indirect brw_indirect_offset( struct brw_indirect ptr, GLint offset ){ ptr.addr_offset += offset; return ptr;}static INLINE struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offset ){ struct brw_indirect ptr; ptr.addr_subnr = addr_subnr; ptr.addr_offset = offset; ptr.pad = 0; return ptr;}static INLINE struct brw_instruction *current_insn( struct brw_compile *p){ return &p->store[p->nr_insn];}void brw_pop_insn_state( struct brw_compile *p );void brw_push_insn_state( struct brw_compile *p );void brw_set_mask_control( struct brw_compile *p, GLuint value );void brw_set_saturate( struct brw_compile *p, GLuint value );void brw_set_access_mode( struct brw_compile *p, GLuint access_mode );void brw_set_compression_control( struct brw_compile *p, GLboolean control );void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value );void brw_set_predicate_control( struct brw_compile *p, GLuint pc );void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional );void brw_init_compile( struct brw_context *, struct brw_compile *p );const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz );/* Helpers for regular instructions: */#define ALU1(OP) \struct brw_instruction *brw_##OP(struct brw_compile *p, \ struct brw_reg dest, \ struct brw_reg src0);#define ALU2(OP) \struct brw_instruction *brw_##OP(struct brw_compile *p, \ struct brw_reg dest, \ struct brw_reg src0, \ struct brw_reg src1);ALU1(MOV)ALU2(SEL)ALU1(NOT)ALU2(AND)ALU2(OR)ALU2(XOR)ALU2(SHR)ALU2(SHL)ALU2(RSR)ALU2(RSL)ALU2(ASR)ALU2(JMPI)ALU2(ADD)ALU2(MUL)ALU1(FRC)ALU1(RNDD)ALU2(MAC)ALU2(MACH)ALU1(LZD)ALU2(DP4)ALU2(DPH)ALU2(DP3)ALU2(DP2)ALU2(LINE)#undef ALU1#undef ALU2/* Helpers for SEND instruction: */void brw_urb_WRITE(struct brw_compile *p, struct brw_reg dest, GLuint msg_reg_nr, struct brw_reg src0, GLboolean allocate, GLboolean used, GLuint msg_length, GLuint response_length, GLboolean eot, GLboolean writes_complete, GLuint offset, GLuint swizzle);void brw_fb_WRITE(struct brw_compile *p, struct brw_reg dest, GLuint msg_reg_nr, struct brw_reg src0, GLuint binding_table_index, GLuint msg_length, GLuint response_length, GLboolean eot);void brw_SAMPLE(struct brw_compile *p, struct brw_reg dest, GLuint msg_reg_nr, struct brw_reg src0, GLuint binding_table_index, GLuint sampler, GLuint writemask, GLuint msg_type, GLuint response_length, GLuint msg_length, GLboolean eot);void brw_math_16( struct brw_compile *p, struct brw_reg dest, GLuint function, GLuint saturate, GLuint msg_reg_nr, struct brw_reg src, GLuint precision );void brw_math( struct brw_compile *p, struct brw_reg dest, GLuint function, GLuint saturate, GLuint msg_reg_nr, struct brw_reg src, GLuint data_type, GLuint precision );void brw_dp_READ_16( struct brw_compile *p, struct brw_reg dest, GLuint msg_reg_nr, GLuint scratch_offset );void brw_dp_WRITE_16( struct brw_compile *p, struct brw_reg src, GLuint msg_reg_nr, GLuint scratch_offset );/* If/else/endif. Works by manipulating the execution flags on each * channel. */struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size);struct brw_instruction *brw_ELSE(struct brw_compile *p, struct brw_instruction *if_insn);void brw_ENDIF(struct brw_compile *p, struct brw_instruction *if_or_else_insn);/* DO/WHILE loops: */struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size);struct brw_instruction *brw_WHILE(struct brw_compile *p, struct brw_instruction *patch_insn);struct brw_instruction *brw_BREAK(struct brw_compile *p);struct brw_instruction *brw_CONT(struct brw_compile *p);/* Forward jumps: */void brw_land_fwd_jump(struct brw_compile *p, struct brw_instruction *jmp_insn);void brw_NOP(struct brw_compile *p);/* Special case: there is never a destination, execution size will be * taken from src0: */void brw_CMP(struct brw_compile *p, struct brw_reg dest, GLuint conditional, struct brw_reg src0, struct brw_reg src1);void brw_print_reg( struct brw_reg reg );/*********************************************************************** * brw_eu_util.c: */void brw_copy_indirect_to_indirect(struct brw_compile *p, struct brw_indirect dst_ptr, struct brw_indirect src_ptr, GLuint count);void brw_copy_from_indirect(struct brw_compile *p, struct brw_reg dst, struct brw_indirect ptr, GLuint count);void brw_copy4(struct brw_compile *p, struct brw_reg dst, struct brw_reg src, GLuint count);void brw_copy8(struct brw_compile *p, struct brw_reg dst, struct brw_reg src, GLuint count);void brw_math_invert( struct brw_compile *p, struct brw_reg dst, struct brw_reg src);void brw_set_src1( struct brw_instruction *insn, struct brw_reg reg );#endif
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