⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 brw_eu.h

📁 Mesa is an open-source implementation of the OpenGL specification - a system for rendering interacti
💻 H
📖 第 1 页 / 共 2 页
字号:
/* Copyright (C) Intel Corp.  2006.  All Rights Reserved. Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to develop this 3D driver.  Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:  The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software.  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  **********************************************************************/ /*  * Authors:  *   Keith Whitwell <keith@tungstengraphics.com>  */   #ifndef BRW_EU_H#define BRW_EU_H#include "brw_structs.h"#include "brw_defines.h"#include "shader/prog_instruction.h"#define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))#define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)#define BRW_SWIZZLE_NOOP      BRW_SWIZZLE4(0,1,2,3)#define BRW_SWIZZLE_XYZW      BRW_SWIZZLE4(0,1,2,3)#define BRW_SWIZZLE_XXXX      BRW_SWIZZLE4(0,0,0,0)#define BRW_SWIZZLE_XYXY      BRW_SWIZZLE4(0,1,0,1)#define REG_SIZE (8*4)/* These aren't hardware structs, just something useful for us to pass around: * * Align1 operation has a lot of control over input ranges.  Used in * WM programs to implement shaders decomposed into "channel serial" * or "structure of array" form: */struct brw_reg{   GLuint type:4;   GLuint file:2;   GLuint nr:8;   GLuint subnr:5;		/* :1 in align16 */   GLuint negate:1;		/* source only */   GLuint abs:1;		/* source only */   GLuint vstride:4;		/* source only */   GLuint width:3;		/* src only, align1 only */   GLuint hstride:2;   		/* src only, align1 only */   GLuint address_mode:1;	/* relative addressing, hopefully! */   GLuint pad0:1;   union {            struct {	 GLuint swizzle:8;		/* src only, align16 only */	 GLuint writemask:4;		/* dest only, align16 only */	 GLint  indirect_offset:10;	/* relative addressing offset */	 GLuint pad1:10;		/* two dwords total */      } bits;      GLfloat f;      GLint   d;      GLuint ud;   } dw1;      };struct brw_indirect {   GLuint addr_subnr:4;   GLint addr_offset:10;   GLuint pad:18;};#define BRW_EU_MAX_INSN_STACK 5#define BRW_EU_MAX_INSN 1200struct brw_compile {   struct brw_instruction store[BRW_EU_MAX_INSN];   GLuint nr_insn;   /* Allow clients to push/pop instruction state:    */   struct brw_instruction stack[BRW_EU_MAX_INSN_STACK];   struct brw_instruction *current;   GLuint flag_value;   GLboolean single_program_flow;   struct brw_context *brw;};static INLINE int type_sz( GLuint type ){   switch( type ) {   case BRW_REGISTER_TYPE_UD:   case BRW_REGISTER_TYPE_D:   case BRW_REGISTER_TYPE_F:      return 4;   case BRW_REGISTER_TYPE_HF:   case BRW_REGISTER_TYPE_UW:   case BRW_REGISTER_TYPE_W:      return 2;   case BRW_REGISTER_TYPE_UB:   case BRW_REGISTER_TYPE_B:      return 1;   default:      return 0;   }}static INLINE struct brw_reg brw_reg( GLuint file,					GLuint nr,					GLuint subnr,					GLuint type,					GLuint vstride,					GLuint width,					GLuint hstride,					GLuint swizzle,					GLuint writemask){         struct brw_reg reg;   reg.type = type;   reg.file = file;   reg.nr = nr;   reg.subnr = subnr * type_sz(type);   reg.negate = 0;   reg.abs = 0;   reg.vstride = vstride;   reg.width = width;   reg.hstride = hstride;   reg.address_mode = BRW_ADDRESS_DIRECT;   reg.pad0 = 0;   /* Could do better: If the reg is r5.3<0;1,0>, we probably want to    * set swizzle and writemask to W, as the lower bits of subnr will    * be lost when converted to align16.  This is probably too much to    * keep track of as you'd want it adjusted by suboffset(), etc.    * Perhaps fix up when converting to align16?    */   reg.dw1.bits.swizzle = swizzle;   reg.dw1.bits.writemask = writemask;   reg.dw1.bits.indirect_offset = 0;   reg.dw1.bits.pad1 = 0;   return reg;}static INLINE struct brw_reg brw_vec16_reg( GLuint file,					      GLuint nr,					      GLuint subnr ){   return brw_reg(file,		  nr,		  subnr,		  BRW_REGISTER_TYPE_F,		  BRW_VERTICAL_STRIDE_16,		  BRW_WIDTH_16,		  BRW_HORIZONTAL_STRIDE_1,		  BRW_SWIZZLE_XYZW,		  WRITEMASK_XYZW);}static INLINE struct brw_reg brw_vec8_reg( GLuint file,					     GLuint nr,					     GLuint subnr ){   return brw_reg(file,		  nr,		  subnr,		  BRW_REGISTER_TYPE_F,		  BRW_VERTICAL_STRIDE_8,		  BRW_WIDTH_8,		  BRW_HORIZONTAL_STRIDE_1,		  BRW_SWIZZLE_XYZW,		  WRITEMASK_XYZW);}static INLINE struct brw_reg brw_vec4_reg( GLuint file,					      GLuint nr,					      GLuint subnr ){   return brw_reg(file,		  nr,		  subnr,		  BRW_REGISTER_TYPE_F,		  BRW_VERTICAL_STRIDE_4,		  BRW_WIDTH_4,		  BRW_HORIZONTAL_STRIDE_1,		  BRW_SWIZZLE_XYZW,		  WRITEMASK_XYZW);}static INLINE struct brw_reg brw_vec2_reg( GLuint file,					      GLuint nr,					      GLuint subnr ){   return brw_reg(file,		  nr,		  subnr,		  BRW_REGISTER_TYPE_F,		  BRW_VERTICAL_STRIDE_2,		  BRW_WIDTH_2,		  BRW_HORIZONTAL_STRIDE_1,		  BRW_SWIZZLE_XYXY,		  WRITEMASK_XY);}static INLINE struct brw_reg brw_vec1_reg( GLuint file,					     GLuint nr,					     GLuint subnr ){   return brw_reg(file,		  nr,		  subnr,		  BRW_REGISTER_TYPE_F,		  BRW_VERTICAL_STRIDE_0,		  BRW_WIDTH_1,		  BRW_HORIZONTAL_STRIDE_0,		  BRW_SWIZZLE_XXXX,		  WRITEMASK_X);}static INLINE struct brw_reg retype( struct brw_reg reg,				       GLuint type ){   reg.type = type;   return reg;}static INLINE struct brw_reg suboffset( struct brw_reg reg,					  GLuint delta ){      reg.subnr += delta * type_sz(reg.type);   return reg;}static INLINE struct brw_reg offset( struct brw_reg reg,				       GLuint delta ){   reg.nr += delta;   return reg;}static INLINE struct brw_reg byte_offset( struct brw_reg reg,					    GLuint bytes ){   GLuint newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;   reg.nr = newoffset / REG_SIZE;   reg.subnr = newoffset % REG_SIZE;   return reg;}   static INLINE struct brw_reg brw_uw16_reg( GLuint file,					     GLuint nr,					     GLuint subnr ){   return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);}static INLINE struct brw_reg brw_uw8_reg( GLuint file,					    GLuint nr,					    GLuint subnr ){   return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);}static INLINE struct brw_reg brw_uw1_reg( GLuint file,					    GLuint nr,					    GLuint subnr ){   return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);}static INLINE struct brw_reg brw_imm_reg( GLuint type ){   return brw_reg( BRW_IMMEDIATE_VALUE,		   0,		   0,		   type,		   BRW_VERTICAL_STRIDE_0,		   BRW_WIDTH_1,		   BRW_HORIZONTAL_STRIDE_0,		   0,		   0);      }static INLINE struct brw_reg brw_imm_f( GLfloat f ){   struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);   imm.dw1.f = f;   return imm;}static INLINE struct brw_reg brw_imm_d( GLint d ){   struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);   imm.dw1.d = d;   return imm;}static INLINE struct brw_reg brw_imm_ud( GLuint ud ){   struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);   imm.dw1.ud = ud;   return imm;}static INLINE struct brw_reg brw_imm_uw( GLushort uw ){   struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);   imm.dw1.ud = uw | (uw << 16);   return imm;}static INLINE struct brw_reg brw_imm_w( GLshort w ){   struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);   imm.dw1.d = w | (w << 16);   return imm;}/* brw_imm_b and brw_imm_ub aren't supported by hardware - the type * numbers alias with _V and _VF below: *//* Vector of eight signed half-byte values:  */static INLINE struct brw_reg brw_imm_v( GLuint v ){   struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);   imm.vstride = BRW_VERTICAL_STRIDE_0;   imm.width = BRW_WIDTH_8;   imm.hstride = BRW_HORIZONTAL_STRIDE_1;   imm.dw1.ud = v;   return imm;}/* Vector of four 8-bit float values: */static INLINE struct brw_reg brw_imm_vf( GLuint v ){   struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);   imm.vstride = BRW_VERTICAL_STRIDE_0;   imm.width = BRW_WIDTH_4;   imm.hstride = BRW_HORIZONTAL_STRIDE_1;   imm.dw1.ud = v;   return imm;}#define VF_ZERO 0x0#define VF_ONE  0x30#define VF_NEG  (1<<7)static INLINE struct brw_reg brw_imm_vf4( GLuint v0, 					    GLuint v1, 					    GLuint v2,					    GLuint v3){   struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);   imm.vstride = BRW_VERTICAL_STRIDE_0;   imm.width = BRW_WIDTH_4;   imm.hstride = BRW_HORIZONTAL_STRIDE_1;   imm.dw1.ud = ((v0 << 0) |		 (v1 << 8) |		 (v2 << 16) |		 (v3 << 24));   return imm;}static INLINE struct brw_reg brw_address( struct brw_reg reg ){   return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);}static INLINE struct brw_reg brw_vec1_grf( GLuint nr,					       GLuint subnr ){   return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);}static INLINE struct brw_reg brw_vec8_grf( GLuint nr,					     GLuint subnr ){   return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);}static INLINE struct brw_reg brw_vec4_grf( GLuint nr,					     GLuint subnr ){   return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);}static INLINE struct brw_reg brw_vec2_grf( GLuint nr,					     GLuint subnr ){   return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);}static INLINE struct brw_reg brw_uw8_grf( GLuint nr,					    GLuint subnr ){   return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);}static INLINE struct brw_reg brw_null_reg( void ){   return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, 		       BRW_ARF_NULL, 		       0);}

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -