📄 brw_structs.h
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/* Copyright (C) Intel Corp. 2006. All Rights Reserved. Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to develop this 3D driver. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. **********************************************************************/ /* * Authors: * Keith Whitwell <keith@tungstengraphics.com> */ #ifndef BRW_STRUCTS_H#define BRW_STRUCTS_H/* Command packets: */struct header { GLuint length:16; GLuint opcode:16; };union header_union{ struct header bits; GLuint dword;};struct brw_3d_control{ struct { GLuint length:8; GLuint notify_enable:1; GLuint pad:3; GLuint wc_flush_enable:1; GLuint depth_stall_enable:1; GLuint operation:2; GLuint opcode:16; } header; struct { GLuint pad:2; GLuint dest_addr_type:1; GLuint dest_addr:29; } dest; GLuint dword2; GLuint dword3; };struct brw_3d_primitive{ struct { GLuint length:8; GLuint pad:2; GLuint topology:5; GLuint indexed:1; GLuint opcode:16; } header; GLuint verts_per_instance; GLuint start_vert_location; GLuint instance_count; GLuint start_instance_location; GLuint base_vert_location; };/* These seem to be passed around as function args, so it works out * better to keep them as #defines: */#define BRW_FLUSH_READ_CACHE 0x1#define BRW_FLUSH_STATE_CACHE 0x2#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8struct brw_mi_flush{ GLuint flags:4; GLuint pad:12; GLuint opcode:16;};struct brw_vf_statistics{ GLuint statistics_enable:1; GLuint pad:15; GLuint opcode:16;};struct brw_binding_table_pointers{ struct header header; GLuint vs; GLuint gs; GLuint clp; GLuint sf; GLuint wm; };struct brw_blend_constant_color{ struct header header; GLfloat blend_constant_color[4]; };struct brw_depthbuffer{ union header_union header; union { struct { GLuint pitch:18; GLuint format:3; GLuint pad:2; GLuint software_tiled_rendering_mode:2; GLuint depth_offset_disable:1; GLuint tile_walk:1; GLuint tiled_surface:1; GLuint pad2:1; GLuint surface_type:3; } bits; GLuint dword; } dword1; GLuint dword2_base_addr; union { struct { GLuint pad:1; GLuint mipmap_layout:1; GLuint lod:4; GLuint width:13; GLuint height:13; } bits; GLuint dword; } dword3; union { struct { GLuint pad:10; GLuint min_array_element:11; GLuint depth:11; } bits; GLuint dword; } dword4;};struct brw_depthbuffer_gm45_g4x{ union header_union header; union { struct { GLuint pitch:18; GLuint format:3; GLuint pad:2; GLuint software_tiled_rendering_mode:2; GLuint depth_offset_disable:1; GLuint tile_walk:1; GLuint tiled_surface:1; GLuint pad2:1; GLuint surface_type:3; } bits; GLuint dword; } dword1; GLuint dword2_base_addr; union { struct { GLuint pad:1; GLuint mipmap_layout:1; GLuint lod:4; GLuint width:13; GLuint height:13; } bits; GLuint dword; } dword3; union { struct { GLuint pad:10; GLuint min_array_element:11; GLuint depth:11; } bits; GLuint dword; } dword4; union { struct { GLuint xoffset:16; GLuint yoffset:16; } bits; GLuint dword; } dword5; /* NEW in Integrated Graphics Device */};struct brw_drawrect{ struct header header; GLuint xmin:16; GLuint ymin:16; GLuint xmax:16; GLuint ymax:16; GLuint xorg:16; GLuint yorg:16; };struct brw_global_depth_offset_clamp{ struct header header; GLfloat depth_offset_clamp; };struct brw_indexbuffer{ union { struct { GLuint length:8; GLuint index_format:2; GLuint cut_index_enable:1; GLuint pad:5; GLuint opcode:16; } bits; GLuint dword; } header; GLuint buffer_start; GLuint buffer_end; };/* NEW in Integrated Graphics Device */struct brw_aa_line_parameters{ struct header header; struct { GLuint aa_coverage_scope:8; GLuint pad0:8; GLuint aa_coverage_bias:8; GLuint pad1:8; } bits0; struct { GLuint aa_coverage_endcap_slope:8; GLuint pad0:8; GLuint aa_coverage_endcap_bias:8; GLuint pad1:8; } bits1;};struct brw_line_stipple{ struct header header; struct { GLuint pattern:16; GLuint pad:16; } bits0; struct { GLuint repeat_count:9; GLuint pad:7; GLuint inverse_repeat_count:16; } bits1;};struct brw_pipelined_state_pointers{ struct header header; struct { GLuint pad:5; GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ } vs; struct { GLuint enable:1; GLuint pad:4; GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ } gs; struct { GLuint enable:1; GLuint pad:4; GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ } clp; struct { GLuint pad:5; GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ } sf; struct { GLuint pad:5; GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ } wm; struct { GLuint pad:5; GLuint offset:27; /* Offset from GENERAL_STATE_BASE. KW: check me! */ } cc;};struct brw_polygon_stipple_offset{ struct header header; struct { GLuint y_offset:5; GLuint pad:3; GLuint x_offset:5; GLuint pad0:19; } bits0;};struct brw_polygon_stipple{ struct header header; GLuint stipple[32];};struct brw_pipeline_select{ struct { GLuint pipeline_select:1; GLuint pad:15; GLuint opcode:16; } header;};struct brw_pipe_control{ struct { GLuint length:8; GLuint notify_enable:1; GLuint texture_cache_flush_enable:1; GLuint indirect_state_pointers_disable:1; GLuint instruction_state_cache_flush_enable:1; GLuint write_cache_flush_enable:1; GLuint depth_stall_enable:1; GLuint post_sync_operation:2; GLuint opcode:16; } header; struct { GLuint pad:2; GLuint dest_addr_type:1; GLuint dest_addr:29; } bits1; GLuint data0; GLuint data1;};struct brw_urb_fence{ struct { GLuint length:8; GLuint vs_realloc:1; GLuint gs_realloc:1; GLuint clp_realloc:1; GLuint sf_realloc:1; GLuint vfe_realloc:1; GLuint cs_realloc:1; GLuint pad:2; GLuint opcode:16; } header; struct { GLuint vs_fence:10; GLuint gs_fence:10; GLuint clp_fence:10; GLuint pad:2; } bits0; struct { GLuint sf_fence:10; GLuint vf_fence:10; GLuint cs_fence:10; GLuint pad:2; } bits1;};struct brw_constant_buffer_state /* previously brw_command_streamer */{ struct header header; struct { GLuint nr_urb_entries:3; GLuint pad:1; GLuint urb_entry_size:5; GLuint pad0:23; } bits0;};struct brw_constant_buffer{ struct { GLuint length:8; GLuint valid:1; GLuint pad:7; GLuint opcode:16; } header; struct { GLuint buffer_length:6; GLuint buffer_address:26; } bits0;};struct brw_state_base_address{ struct header header; struct { GLuint modify_enable:1; GLuint pad:4; GLuint general_state_address:27; } bits0; struct { GLuint modify_enable:1; GLuint pad:4; GLuint surface_state_address:27; } bits1; struct { GLuint modify_enable:1; GLuint pad:4; GLuint indirect_object_state_address:27; } bits2; struct { GLuint modify_enable:1; GLuint pad:11; GLuint general_state_upper_bound:20; } bits3; struct { GLuint modify_enable:1; GLuint pad:11; GLuint indirect_object_state_upper_bound:20; } bits4;};struct brw_state_prefetch{ struct header header; struct { GLuint prefetch_count:3; GLuint pad:3; GLuint prefetch_pointer:26; } bits0;};struct brw_system_instruction_pointer{ struct header header; struct { GLuint pad:4; GLuint system_instruction_pointer:28; } bits0;};/* State structs for the various fixed function units: */struct thread0{ GLuint pad0:1; GLuint grf_reg_count:3; GLuint pad1:2; GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */};struct thread1{ GLuint ext_halt_exception_enable:1; GLuint sw_exception_enable:1; GLuint mask_stack_exception_enable:1; GLuint timeout_exception_enable:1; GLuint illegal_op_exception_enable:1; GLuint pad0:3; GLuint depth_coef_urb_read_offset:6; /* WM only */ GLuint pad1:2; GLuint floating_point_mode:1; GLuint thread_priority:1; GLuint binding_table_entry_count:8; GLuint pad3:5; GLuint single_program_flow:1; };struct thread2{ GLuint per_thread_scratch_space:4; GLuint pad0:6; GLuint scratch_space_base_pointer:22; }; struct thread3{ GLuint dispatch_grf_start_reg:4; GLuint urb_entry_read_offset:6; GLuint pad0:1; GLuint urb_entry_read_length:6; GLuint pad1:1; GLuint const_urb_entry_read_offset:6; GLuint pad2:1; GLuint const_urb_entry_read_length:6; GLuint pad3:1;};struct brw_clip_unit_state{ struct thread0 thread0; struct { GLuint pad0:7; GLuint sw_exception_enable:1; GLuint pad1:3; GLuint mask_stack_exception_enable:1; GLuint pad2:1; GLuint illegal_op_exception_enable:1; GLuint pad3:2; GLuint floating_point_mode:1; GLuint thread_priority:1; GLuint binding_table_entry_count:8; GLuint pad4:5; GLuint single_program_flow:1; } thread1; struct thread2 thread2; struct thread3 thread3; struct { GLuint pad0:9; GLuint gs_output_stats:1; /* not always */ GLuint stats_enable:1; GLuint nr_urb_entries:7; GLuint pad1:1; GLuint urb_entry_allocation_size:5; GLuint pad2:1; GLuint max_threads:5; /* may be less */ GLuint pad3:2; } thread4; struct { GLuint pad0:13; GLuint clip_mode:3; GLuint userclip_enable_flags:8; GLuint userclip_must_clip:1; GLuint negative_w_clip_test:1; GLuint guard_band_enable:1; GLuint viewport_z_clip_enable:1; GLuint viewport_xy_clip_enable:1; GLuint vertex_position_space:1; GLuint api_mode:1; GLuint pad2:1; } clip5; struct { GLuint pad0:5; GLuint clipper_viewport_state_ptr:27; } clip6; GLfloat viewport_xmin; GLfloat viewport_xmax; GLfloat viewport_ymin; GLfloat viewport_ymax; };struct brw_cc_unit_state{ struct { GLuint pad0:3; GLuint bf_stencil_pass_depth_pass_op:3; GLuint bf_stencil_pass_depth_fail_op:3; GLuint bf_stencil_fail_op:3; GLuint bf_stencil_func:3; GLuint bf_stencil_enable:1; GLuint pad1:2; GLuint stencil_write_enable:1; GLuint stencil_pass_depth_pass_op:3; GLuint stencil_pass_depth_fail_op:3; GLuint stencil_fail_op:3; GLuint stencil_func:3; GLuint stencil_enable:1; } cc0; struct { GLuint bf_stencil_ref:8; GLuint stencil_write_mask:8; GLuint stencil_test_mask:8; GLuint stencil_ref:8; } cc1; struct { GLuint logicop_enable:1; GLuint pad0:10; GLuint depth_write_enable:1; GLuint depth_test_function:3; GLuint depth_test:1; GLuint bf_stencil_write_mask:8; GLuint bf_stencil_test_mask:8; } cc2; struct { GLuint pad0:8; GLuint alpha_test_func:3; GLuint alpha_test:1; GLuint blend_enable:1; GLuint ia_blend_enable:1; GLuint pad1:1; GLuint alpha_test_format:1; GLuint pad2:16; } cc3; struct { GLuint pad0:5; GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ } cc4; struct { GLuint pad0:2; GLuint ia_dest_blend_factor:5; GLuint ia_src_blend_factor:5; GLuint ia_blend_function:3; GLuint statistics_enable:1; GLuint logicop_func:4; GLuint pad1:11; GLuint dither_enable:1; } cc5; struct {
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