via_dri.c

Mesa is an open-source implementation of the OpenGL specification - a system for rendering interacti

        VIADRIPciInit(ctx, pVia);
	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use pci.\n" );
    }
    else
        xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use agp.\n" );

    if (!(VIADRIFBInit(ctx, pVia))) {
	VIADRICloseScreen(ctx);
        xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[dri] frame buffer initialize fail .\n" );
        return GL_FALSE;
    }
    
    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] frame buffer initialized.\n" );
 
    return VIADRIFinishScreenInit(ctx);
}

static void
VIADRICloseScreen(DRIDriverContext * ctx)
{
    VIAPtr pVia = VIAPTR(ctx);
    VIADRIPtr pVIADRI=(VIADRIPtr)pVia->devPrivate;

    VIADRIRingBufferCleanup(ctx);

    if (pVia->MapBase) {
	xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Unmapping MMIO registers\n");
        drmUnmap(pVia->MapBase, pVIADRI->regs.size);
    }

    if (pVia->agpSize) {
	xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Freeing agp memory\n");
        drmAgpFree(pVia->drmFD, pVia->agpHandle);
	xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Releasing agp module\n");
    	drmAgpRelease(pVia->drmFD);
    }

#if 0
    if (pVia->DRIIrqEnable) 
#endif
        VIADRIIrqExit(ctx);
}

static int
VIADRIFinishScreenInit(DRIDriverContext * ctx)
{
    VIAPtr pVia = VIAPTR(ctx);
    VIADRIPtr pVIADRI;
    int err;

    err = drmCreateContext(ctx->drmFD, &ctx->serverContext);
    if (err != 0) {
        fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
        return GL_FALSE;
    }

    DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0);


    if (!VIADRIKernelInit(ctx, pVia)) {
	VIADRICloseScreen(ctx);
	return GL_FALSE;
    }
    xf86DrvMsg(pScreen->myNum, X_INFO, "[dri] kernel data initialized.\n");

    /* set SAREA value */
    {
	drm_via_sarea_t *saPriv;

	saPriv=(drm_via_sarea_t*)(((char*)ctx->pSAREA) +
                               sizeof(drm_sarea_t));
	assert(saPriv);
	memset(saPriv, 0, sizeof(*saPriv));
	saPriv->ctxOwner = -1;
    }
    pVIADRI=(VIADRIPtr)pVia->devPrivate;
    pVIADRI->deviceID=pVia->Chipset;  
    pVIADRI->width=ctx->shared.virtualWidth;
    pVIADRI->height=ctx->shared.virtualHeight;
    pVIADRI->mem=ctx->shared.fbSize;
    pVIADRI->bytesPerPixel= (ctx->bpp+7) / 8; 
    pVIADRI->sarea_priv_offset = sizeof(drm_sarea_t);
    /* TODO */
    pVIADRI->scrnX=pVIADRI->width;
    pVIADRI->scrnY=pVIADRI->height;

    /* Initialize IRQ */
#if 0
    if (pVia->DRIIrqEnable) 
#endif
	VIADRIIrqInit(ctx);
    
    pVIADRI->ringBufActive = 0;
    VIADRIRingBufferInit(ctx);

    return GL_TRUE;
}

/* Initialize the kernel data structures. */
static int VIADRIKernelInit(DRIDriverContext * ctx, VIAPtr pVia)
{
    drm_via_init_t drmInfo;
    memset(&drmInfo, 0, sizeof(drm_via_init_t));
    drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
    drmInfo.func = VIA_INIT_MAP;
    drmInfo.fb_offset           = pVia->FrameBufferBase;
    drmInfo.mmio_offset         = pVia->registerHandle;
    if (pVia->IsPCI)
	drmInfo.agpAddr = (u_int32_t)NULL;
    else
	drmInfo.agpAddr = (u_int32_t)pVia->agpAddr;

    if ((drmCommandWrite(pVia->drmFD, DRM_VIA_MAP_INIT,&drmInfo,
			     sizeof(drm_via_init_t))) < 0)
	    return GL_FALSE;

    return GL_TRUE;
}
/* Add a map for the MMIO registers */
static int VIADRIMapInit(DRIDriverContext * ctx, VIAPtr pVia)
{
    int flags = 0;

    if (drmAddMap(pVia->drmFD, pVia->MmioBase, VIA_MMIO_REGSIZE,
		  DRM_REGISTERS, flags, &pVia->registerHandle) < 0) {
	return GL_FALSE;
    }

    xf86DrvMsg(pScreen->myNum, X_INFO,
	"[drm] register handle = 0x%08lx\n", pVia->registerHandle);

    return GL_TRUE;
}

static int viaValidateMode(const DRIDriverContext *ctx)
{
    VIAPtr pVia = VIAPTR(ctx);

    return 1;
}

static int viaPostValidateMode(const DRIDriverContext *ctx)
{
    VIAPtr pVia = VIAPTR(ctx);

    return 1;
}

static void VIAEnableMMIO(DRIDriverContext * ctx)
{
    /*vgaHWPtr hwp = VGAHWPTR(ctx);*/
    VIAPtr pVia = VIAPTR(ctx);
    unsigned char val;

#if 0
    if (xf86IsPrimaryPci(pVia->PciInfo)) {
        /* If we are primary card, we still use std vga port. If we use
         * MMIO, system will hang in vgaHWSave when our card used in
         * PLE and KLE (integrated Trident MVP4)
         */
        vgaHWSetStdFuncs(hwp);
    }
    else {
        vgaHWSetMmioFuncs(hwp, pVia->MapBase, 0x8000);
    }
#endif

    val = VGAIN8(0x3c3);
    VGAOUT8(0x3c3, val | 0x01);
    val = VGAIN8(0x3cc);
    VGAOUT8(0x3c2, val | 0x01);

    /* Unlock Extended IO Space */
    VGAOUT8(0x3c4, 0x10);
    VGAOUT8(0x3c5, 0x01);

    /* Enable MMIO */
    if(!pVia->IsSecondary) {
	VGAOUT8(0x3c4, 0x1a);
	val = VGAIN8(0x3c5);
#ifdef DEBUG
	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "primary val = %x\n", val);
#endif
	VGAOUT8(0x3c5, val | 0x68);
    }
    else {
	VGAOUT8(0x3c4, 0x1a);
	val = VGAIN8(0x3c5);
#ifdef DEBUG
	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "secondary val = %x\n", val);
#endif
	VGAOUT8(0x3c5, val | 0x38);
    }

    /* Unlock CRTC registers */
    VGAOUT8(0x3d4, 0x47);
    VGAOUT8(0x3d5, 0x00);

    return;
}

static void VIADisableMMIO(DRIDriverContext * ctx)
{
    VIAPtr pVia = VIAPTR(ctx);
    unsigned char val;

    VGAOUT8(0x3c4, 0x1a);
    val = VGAIN8(0x3c5);
    VGAOUT8(0x3c5, val & 0x97);

    return;
}

static void VIADisableExtendedFIFO(DRIDriverContext *ctx)
{
    VIAPtr  pVia = VIAPTR(ctx);
    u_int32_t  dwGE230, dwGE298;

    /* Cause of exit XWindow will dump back register value, others chipset no
     * need to set extended fifo value */
    if (pVia->Chipset == VIA_CLE266 && pVia->ChipRev < 15 &&
        (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary)) {
        /* Turn off Extend FIFO */
        /* 0x298[29] */
        dwGE298 = VIAGETREG(0x298);
        VIASETREG(0x298, dwGE298 | 0x20000000);
        /* 0x230[21] */
        dwGE230 = VIAGETREG(0x230);
        VIASETREG(0x230, dwGE230 & ~0x00200000);
        /* 0x298[29] */
        dwGE298 = VIAGETREG(0x298);
        VIASETREG(0x298, dwGE298 & ~0x20000000);
    }
}

static void VIAEnableExtendedFIFO(DRIDriverContext *ctx)
{
    VIAPtr  pVia = VIAPTR(ctx);
    u_int8_t   bRegTemp;
    u_int32_t  dwGE230, dwGE298;

    switch (pVia->Chipset) {
    case VIA_CLE266:
        if (pVia->ChipRev > 14) {  /* For 3123Cx */
            if (pVia->HasSecondary) {  /* SAMM or DuoView case */
                if (ctx->shared.virtualWidth >= 1024)
    	        {
    	            /* 3c5.16[0:5] */
        	        VGAOUT8(0x3C4, 0x16);
            	    bRegTemp = VGAIN8(0x3C5);
    	            bRegTemp &= ~0x3F;
        	        bRegTemp |= 0x1C;
            	    VGAOUT8(0x3C5, bRegTemp);
        	        /* 3c5.17[0:6] */
            	    VGAOUT8(0x3C4, 0x17);
                	bRegTemp = VGAIN8(0x3C5);
    	            bRegTemp &= ~0x7F;
        	        bRegTemp |= 0x3F;
            	    VGAOUT8(0x3C5, bRegTemp);
            	    pVia->EnableExtendedFIFO = GL_TRUE;
    	        }
            }
            else   /* Single view or Simultaneoue case */
            {
                if (ctx->shared.virtualWidth > 1024)
    	        {
    	            /* 3c5.16[0:5] */
        	        VGAOUT8(0x3C4, 0x16);
            	    bRegTemp = VGAIN8(0x3C5);
    	            bRegTemp &= ~0x3F;
        	        bRegTemp |= 0x17;
            	    VGAOUT8(0x3C5, bRegTemp);
        	        /* 3c5.17[0:6] */
            	    VGAOUT8(0x3C4, 0x17);
                	bRegTemp = VGAIN8(0x3C5);
    	            bRegTemp &= ~0x7F;
        	        bRegTemp |= 0x2F;
            	    VGAOUT8(0x3C5, bRegTemp);
            	    pVia->EnableExtendedFIFO = GL_TRUE;
    	        }
            }
            /* 3c5.18[0:5] */
            VGAOUT8(0x3C4, 0x18);
            bRegTemp = VGAIN8(0x3C5);
            bRegTemp &= ~0x3F;
            bRegTemp |= 0x17;
            bRegTemp |= 0x40;  /* force the preq always higher than treq */
            VGAOUT8(0x3C5, bRegTemp);
        }
        else {      /* for 3123Ax */
            if (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary) {
                /* Turn on Extend FIFO */
                /* 0x298[29] */
                dwGE298 = VIAGETREG(0x298);
                VIASETREG(0x298, dwGE298 | 0x20000000);
                /* 0x230[21] */
                dwGE230 = VIAGETREG(0x230);
                VIASETREG(0x230, dwGE230 | 0x00200000);
                /* 0x298[29] */
                dwGE298 = VIAGETREG(0x298);
                VIASETREG(0x298, dwGE298 & ~0x20000000);

                /* 3c5.16[0:5] */
                VGAOUT8(0x3C4, 0x16);
                bRegTemp = VGAIN8(0x3C5);
                bRegTemp &= ~0x3F;
                bRegTemp |= 0x17;
                /* bRegTemp |= 0x10; */
                VGAOUT8(0x3C5, bRegTemp);
                /* 3c5.17[0:6] */
                VGAOUT8(0x3C4, 0x17);
                bRegTemp = VGAIN8(0x3C5);
                bRegTemp &= ~0x7F;
                bRegTemp |= 0x2F;
                /*bRegTemp |= 0x1F;*/
                VGAOUT8(0x3C5, bRegTemp);
                /* 3c5.18[0:5] */
                VGAOUT8(0x3C4, 0x18);
                bRegTemp = VGAIN8(0x3C5);
                bRegTemp &= ~0x3F;
                bRegTemp |= 0x17;
                bRegTemp |= 0x40;  /* force the preq always higher than treq */
                VGAOUT8(0x3C5, bRegTemp);
          	    pVia->EnableExtendedFIFO = GL_TRUE;
            }
        }
        break;
    case VIA_KM400:
        if (pVia->HasSecondary) {  /* SAMM or DuoView case */
            if ((ctx->shared.virtualWidth >= 1600) &&
                (pVia->MemClk <= VIA_MEM_DDR200)) {
        	    /* enable CRT extendded FIFO */
            	VGAOUT8(0x3C4, 0x17);
                VGAOUT8(0x3C5, 0x1C);
    	        /* revise second display queue depth and read threshold */
        	    VGAOUT8(0x3C4, 0x16);
            	bRegTemp = VGAIN8(0x3C5);
    	        bRegTemp &= ~0x3F;
    	        bRegTemp = (bRegTemp) | (0x09);
                VGAOUT8(0x3C5, bRegTemp);
            }
            else {
                /* enable CRT extendded FIFO */
                VGAOUT8(0x3C4, 0x17);
                VGAOUT8(0x3C5,0x3F);
                /* revise second display queue depth and read threshold */
                VGAOUT8(0x3C4, 0x16);
                bRegTemp = VGAIN8(0x3C5);
                bRegTemp &= ~0x3F;
                bRegTemp = (bRegTemp) | (0x1C);
                VGAOUT8(0x3C5, bRegTemp);
            }
            /* 3c5.18[0:5] */
            VGAOUT8(0x3C4, 0x18);
            bRegTemp = VGAIN8(0x3C5);
            bRegTemp &= ~0x3F;
            bRegTemp |= 0x17;
            bRegTemp |= 0x40;  /* force the preq always higher than treq */
            VGAOUT8(0x3C5, bRegTemp);
       	    pVia->EnableExtendedFIFO = GL_TRUE;
        }
        else {
            if ( (ctx->shared.virtualWidth > 1024) && (ctx->shared.virtualWidth <= 1280) )
            {
                /* enable CRT extendded FIFO */
                VGAOUT8(0x3C4, 0x17);
                VGAOUT8(0x3C5, 0x3F);
                /* revise second display queue depth and read threshold */
                VGAOUT8(0x3C4, 0x16);
                bRegTemp = VGAIN8(0x3C5);
                bRegTemp &= ~0x3F;
                bRegTemp = (bRegTemp) | (0x17);
                VGAOUT8(0x3C5, bRegTemp);
           	    pVia->EnableExtendedFIFO = GL_TRUE;
            }
            else if ((ctx->shared.virtualWidth > 1280))
            {
                /* enable CRT extendded FIFO */
                VGAOUT8(0x3C4, 0x17);
                VGAOUT8(0x3C5, 0x3F);
                /* revise second display queue depth and read threshold */
                VGAOUT8(0x3C4, 0x16);
                bRegTemp = VGAIN8(0x3C5);
                bRegTemp &= ~0x3F;
                bRegTemp = (bRegTemp) | (0x1C);
                VGAOUT8(0x3C5, bRegTemp);
           	    pVia->EnableExtendedFIFO = GL_TRUE;
            }
            else
            {
                /* enable CRT extendded FIFO */
                VGAOUT8(0x3C4, 0x17);
                VGAOUT8(0x3C5, 0x3F);
                /* revise second display queue depth and read threshold */
                VGAOUT8(0x3C4, 0x16);
                bRegTemp = VGAIN8(0x3C5);
                bRegTemp &= ~0x3F;
                bRegTemp = (bRegTemp) | (0x10);
                VGAOUT8(0x3C5, bRegTemp);
            }
            /* 3c5.18[0:5] */
            VGAOUT8(0x3C4, 0x18);
            bRegTemp = VGAIN8(0x3C5);
            bRegTemp &= ~0x3F;
            bRegTemp |= 0x17;
            bRegTemp |= 0x40;  /* force the preq always higher than treq */
            VGAOUT8(0x3C5, bRegTemp);
        }
        break;
    case VIA_K8M800:
        /*=* R1 Display FIFO depth (384 /8 -1 -> 0xbf) SR17[7:0] (8bits) *=*/
        VGAOUT8(0x3c4, 0x17);
        VGAOUT8(0x3c5, 0xbf);

        /*=* R2 Display fetch datum threshold value (328/4 -> 0x52)
             SR16[5:0], SR16[7] (7bits) *=*/
        VGAOUT8(0x3c4, 0x16);
        bRegTemp = VGAIN8(0x3c5) & ~0xBF;