radeon_program_alu.c

Mesa is an open-source implementation of the OpenGL specification - a system for rendering interacti

/*
 * Copyright (C) 2008 Nicolai Haehnle.
 *
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

/**
 * @file
 *
 * Shareable transformations that transform "special" ALU instructions
 * into ALU instructions that are supported by hardware.
 *
 */

#include "radeon_program_alu.h"

#include "shader/prog_parameter.h"


static struct prog_instruction *emit1(struct gl_program* p,
	gl_inst_opcode Opcode, GLuint Saturate, struct prog_dst_register DstReg,
	struct prog_src_register SrcReg)
{
	struct prog_instruction *fpi = radeonAppendInstructions(p, 1);

	fpi->Opcode = Opcode;
	fpi->SaturateMode = Saturate;
	fpi->DstReg = DstReg;
	fpi->SrcReg[0] = SrcReg;
	return fpi;
}

static struct prog_instruction *emit2(struct gl_program* p,
	gl_inst_opcode Opcode, GLuint Saturate, struct prog_dst_register DstReg,
	struct prog_src_register SrcReg0, struct prog_src_register SrcReg1)
{
	struct prog_instruction *fpi = radeonAppendInstructions(p, 1);

	fpi->Opcode = Opcode;
	fpi->SaturateMode = Saturate;
	fpi->DstReg = DstReg;
	fpi->SrcReg[0] = SrcReg0;
	fpi->SrcReg[1] = SrcReg1;
	return fpi;
}

static struct prog_instruction *emit3(struct gl_program* p,
	gl_inst_opcode Opcode, GLuint Saturate, struct prog_dst_register DstReg,
	struct prog_src_register SrcReg0, struct prog_src_register SrcReg1,
	struct prog_src_register SrcReg2)
{
	struct prog_instruction *fpi = radeonAppendInstructions(p, 1);

	fpi->Opcode = Opcode;
	fpi->SaturateMode = Saturate;
	fpi->DstReg = DstReg;
	fpi->SrcReg[0] = SrcReg0;
	fpi->SrcReg[1] = SrcReg1;
	fpi->SrcReg[2] = SrcReg2;
	return fpi;
}

static void set_swizzle(struct prog_src_register *SrcReg, int coordinate, int swz)
{
	SrcReg->Swizzle &= ~(7 << (3*coordinate));
	SrcReg->Swizzle |= swz << (3*coordinate);
}

static void set_negate_base(struct prog_src_register *SrcReg, int coordinate, int negate)
{
	SrcReg->NegateBase &= ~(1 << coordinate);
	SrcReg->NegateBase |= (negate << coordinate);
}

static struct prog_dst_register dstreg(int file, int index)
{
	struct prog_dst_register dst;
	dst.File = file;
	dst.Index = index;
	dst.WriteMask = WRITEMASK_XYZW;
	dst.CondMask = COND_TR;
	dst.CondSwizzle = SWIZZLE_NOOP;
	dst.CondSrc = 0;
	dst.pad = 0;
	return dst;
}

static struct prog_dst_register dstregtmpmask(int index, int mask)
{
	struct prog_dst_register dst;
	dst.File = PROGRAM_TEMPORARY;
	dst.Index = index;
	dst.WriteMask = mask;
	dst.CondMask = COND_TR;
	dst.CondSwizzle = SWIZZLE_NOOP;
	dst.CondSrc = 0;
	dst.pad = 0;
	return dst;
}

static const struct prog_src_register builtin_zero = {
	.File = PROGRAM_BUILTIN,
	.Index = 0,
	.Swizzle = SWIZZLE_0000
};
static const struct prog_src_register builtin_one = {
	.File = PROGRAM_BUILTIN,
	.Index = 0,
	.Swizzle = SWIZZLE_1111
};
static const struct prog_src_register srcreg_undefined = {
	.File = PROGRAM_UNDEFINED,
	.Index = 0,
	.Swizzle = SWIZZLE_NOOP
};

static struct prog_src_register srcreg(int file, int index)
{
	struct prog_src_register src = srcreg_undefined;
	src.File = file;
	src.Index = index;
	return src;
}

static struct prog_src_register srcregswz(int file, int index, int swz)
{
	struct prog_src_register src = srcreg_undefined;
	src.File = file;
	src.Index = index;
	src.Swizzle = swz;
	return src;
}

static struct prog_src_register absolute(struct prog_src_register reg)
{
	struct prog_src_register newreg = reg;
	newreg.Abs = 1;
	newreg.NegateBase = 0;
	newreg.NegateAbs = 0;
	return newreg;
}

static struct prog_src_register negate(struct prog_src_register reg)
{
	struct prog_src_register newreg = reg;
	newreg.NegateAbs = !newreg.NegateAbs;
	return newreg;
}

static struct prog_src_register swizzle(struct prog_src_register reg, GLuint x, GLuint y, GLuint z, GLuint w)
{
	struct prog_src_register swizzled = reg;
	swizzled.Swizzle = MAKE_SWIZZLE4(
		x >= 4 ? x : GET_SWZ(reg.Swizzle, x),
		y >= 4 ? y : GET_SWZ(reg.Swizzle, y),
		z >= 4 ? z : GET_SWZ(reg.Swizzle, z),
		w >= 4 ? w : GET_SWZ(reg.Swizzle, w));
	return swizzled;
}

static struct prog_src_register scalar(struct prog_src_register reg)
{
	return swizzle(reg, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X);
}

static void transform_ABS(struct radeon_transform_context* t,
	struct prog_instruction* inst)
{
	struct prog_src_register src = inst->SrcReg[0];
	src.Abs = 1;
	src.NegateBase = 0;
	src.NegateAbs = 0;
	emit1(t->Program, OPCODE_MOV, inst->SaturateMode, inst->DstReg, src);
}

static void transform_DPH(struct radeon_transform_context* t,
	struct prog_instruction* inst)
{
	struct prog_src_register src0 = inst->SrcReg[0];
	if (src0.NegateAbs) {
		if (src0.Abs) {
			int tempreg = radeonFindFreeTemporary(t);
			emit1(t->Program, OPCODE_MOV, 0, dstreg(PROGRAM_TEMPORARY, tempreg), src0);
			src0 = srcreg(src0.File, src0.Index);
		} else {
			src0.NegateAbs = 0;
			src0.NegateBase ^= NEGATE_XYZW;
		}
	}
	set_swizzle(&src0, 3, SWIZZLE_ONE);
	set_negate_base(&src0, 3, 0);
	emit2(t->Program, OPCODE_DP4, inst->SaturateMode, inst->DstReg, src0, inst->SrcReg[1]);
}

/**
 * [1, src0.y*src1.y, src0.z, src1.w]
 * So basically MUL with lotsa swizzling.
 */
static void transform_DST(struct radeon_transform_context* t,
	struct prog_instruction* inst)
{
	emit2(t->Program, OPCODE_MUL, inst->SaturateMode, inst->DstReg,
		swizzle(inst->SrcReg[0], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE),
		swizzle(inst->SrcReg[1], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_ONE, SWIZZLE_W));
}

static void transform_FLR(struct radeon_transform_context* t,
	struct prog_instruction* inst)
{
	int tempreg = radeonFindFreeTemporary(t);
	emit1(t->Program, OPCODE_FRC, 0, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0]);
	emit2(t->Program, OPCODE_ADD, inst->SaturateMode, inst->DstReg,
		inst->SrcReg[0], negate(srcreg(PROGRAM_TEMPORARY, tempreg)));
}

/**
 * Definition of LIT (from ARB_fragment_program):
 *
 *  tmp = VectorLoad(op0);
 *  if (tmp.x < 0) tmp.x = 0;
 *  if (tmp.y < 0) tmp.y = 0;
 *  if (tmp.w < -(128.0-epsilon)) tmp.w = -(128.0-epsilon);
 *  else if (tmp.w > 128-epsilon) tmp.w = 128-epsilon;
 *  result.x = 1.0;
 *  result.y = tmp.x;
 *  result.z = (tmp.x > 0) ? RoughApproxPower(tmp.y, tmp.w) : 0.0;
 *  result.w = 1.0;
 *
 * The longest path of computation is the one leading to result.z,
 * consisting of 5 operations. This implementation of LIT takes
 * 5 slots, if the subsequent optimization passes are clever enough
 * to pair instructions correctly.
 */
static void transform_LIT(struct radeon_transform_context* t,
	struct prog_instruction* inst)
{
	static const GLfloat LitConst[4] = { -127.999999 };

	GLuint constant;
	GLuint constant_swizzle;
	GLuint temp;
	int needTemporary = 0;
	struct prog_src_register srctemp;

	constant = _mesa_add_unnamed_constant(t->Program->Parameters, LitConst, 1, &constant_swizzle);

	if (inst->DstReg.WriteMask != WRITEMASK_XYZW) {
		needTemporary = 1;
	} else if (inst->DstReg.File != PROGRAM_TEMPORARY) {
		// LIT is typically followed by DP3/DP4, so there's no point
		// in creating special code for this case
		needTemporary = 1;
	}

	if (needTemporary) {
		temp = radeonFindFreeTemporary(t);
	} else {
		temp = inst->DstReg.Index;
	}
	srctemp = srcreg(PROGRAM_TEMPORARY, temp);

	// tmp.x = max(0.0, Src.x);
	// tmp.y = max(0.0, Src.y);
	// tmp.w = clamp(Src.z, -128+eps, 128-eps);
	emit2(t->Program, OPCODE_MAX, 0,
		dstregtmpmask(temp, WRITEMASK_XYW),
		inst->SrcReg[0],
		swizzle(srcreg(PROGRAM_CONSTANT, constant),
			SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO, constant_swizzle&3));
	emit2(t->Program, OPCODE_MIN, 0,
		dstregtmpmask(temp, WRITEMASK_Z),
		swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
		negate(srcregswz(PROGRAM_CONSTANT, constant, constant_swizzle)));

	// tmp.w = Pow(tmp.y, tmp.w)
	emit1(t->Program, OPCODE_LG2, 0,
		dstregtmpmask(temp, WRITEMASK_W),
		swizzle(srctemp, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y));
	emit2(t->Program, OPCODE_MUL, 0,
		dstregtmpmask(temp, WRITEMASK_W),
		swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
		swizzle(srctemp, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z));
	emit1(t->Program, OPCODE_EX2, 0,
		dstregtmpmask(temp, WRITEMASK_W),
		swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));

	// tmp.z = (tmp.x > 0) ? tmp.w : 0.0
	emit3(t->Program, OPCODE_CMP, inst->SaturateMode,
		dstregtmpmask(temp, WRITEMASK_Z),
		negate(swizzle(srctemp, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
		swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
		builtin_zero);

	// tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0
	emit1(t->Program, OPCODE_MOV, inst->SaturateMode,
		dstregtmpmask(temp, WRITEMASK_XYW),
		swizzle(srctemp, SWIZZLE_ONE, SWIZZLE_X, SWIZZLE_ONE, SWIZZLE_ONE));

	if (needTemporary)
		emit1(t->Program, OPCODE_MOV, 0, inst->DstReg, srctemp);
}

static void transform_LRP(struct radeon_transform_context* t,
	struct prog_instruction* inst)
{
	int tempreg = radeonFindFreeTemporary(t);

	emit2(t->Program, OPCODE_ADD, 0,
		dstreg(PROGRAM_TEMPORARY, tempreg),