r200_sanity.c

Mesa is an open-source implementation of the OpenGL specification - a system for rendering interacti

   { R200_PP_TXFILTER_0, "R200_PP_TXFILTER_0" },
   { R200_PP_TXFORMAT_0, "R200_PP_TXFORMAT_0" },
   { R200_PP_TXSIZE_0, "R200_PP_TXSIZE_0" },
   { R200_PP_TXFORMAT_X_0, "R200_PP_TXFORMAT_X_0" },
   { R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" },
   { R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" },
   { R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" },
   { R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" },
   { R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" },
   { R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" },
   { R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" },
   { R200_PP_TXFORMAT_X_1, "R200_PP_TXFORMAT_X_1" },
   { R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" },
   { R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" },
   { R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" },
   { R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" },
   { R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" },
   { R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" },
   { R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" },
   { R200_PP_TXFORMAT_X_2, "R200_PP_TXFORMAT_X_2" },
   { R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" },
   { R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" },
   { R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" },
   { R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" },
   { R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" },
   { R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" },
   { R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" },
   { R200_PP_TXFORMAT_X_3, "R200_PP_TXFORMAT_X_3" },
   { R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" },
   { R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" },
   { R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" },
   { R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" },
   { R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" },
   { R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" },
   { R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" },
   { R200_PP_TXFORMAT_X_4, "R200_PP_TXFORMAT_X_4" },
   { R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" },
   { R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" },
   { R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" },
   { R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" },
   { R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" },
   { R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" },
   { R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" },
   { R200_PP_TXFORMAT_X_5, "R200_PP_TXFORMAT_X_5" },
   { R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" },
   { R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" },
   { R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" },
   { R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" },
   { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
   { R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" },
   { R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" },
   { R200_PP_CUBIC_OFFSET_F3_0, "R200_PP_CUBIC_OFFSET_F3_0" },
   { R200_PP_CUBIC_OFFSET_F4_0, "R200_PP_CUBIC_OFFSET_F4_0" },
   { R200_PP_CUBIC_OFFSET_F5_0, "R200_PP_CUBIC_OFFSET_F5_0" },
   { R200_PP_TXOFFSET_1, "R200_PP_TXOFFSET_1" },
   { R200_PP_CUBIC_OFFSET_F1_1, "R200_PP_CUBIC_OFFSET_F1_1" },
   { R200_PP_CUBIC_OFFSET_F2_1, "R200_PP_CUBIC_OFFSET_F2_1" },
   { R200_PP_CUBIC_OFFSET_F3_1, "R200_PP_CUBIC_OFFSET_F3_1" },
   { R200_PP_CUBIC_OFFSET_F4_1, "R200_PP_CUBIC_OFFSET_F4_1" },
   { R200_PP_CUBIC_OFFSET_F5_1, "R200_PP_CUBIC_OFFSET_F5_1" },
   { R200_PP_TXOFFSET_2, "R200_PP_TXOFFSET_2" },
   { R200_PP_CUBIC_OFFSET_F1_2, "R200_PP_CUBIC_OFFSET_F1_2" },
   { R200_PP_CUBIC_OFFSET_F2_2, "R200_PP_CUBIC_OFFSET_F2_2" },
   { R200_PP_CUBIC_OFFSET_F3_2, "R200_PP_CUBIC_OFFSET_F3_2" },
   { R200_PP_CUBIC_OFFSET_F4_2, "R200_PP_CUBIC_OFFSET_F4_2" },
   { R200_PP_CUBIC_OFFSET_F5_2, "R200_PP_CUBIC_OFFSET_F5_2" },
   { R200_PP_TXOFFSET_3, "R200_PP_TXOFFSET_3" },
   { R200_PP_CUBIC_OFFSET_F1_3, "R200_PP_CUBIC_OFFSET_F1_3" },
   { R200_PP_CUBIC_OFFSET_F2_3, "R200_PP_CUBIC_OFFSET_F2_3" },
   { R200_PP_CUBIC_OFFSET_F3_3, "R200_PP_CUBIC_OFFSET_F3_3" },
   { R200_PP_CUBIC_OFFSET_F4_3, "R200_PP_CUBIC_OFFSET_F4_3" },
   { R200_PP_CUBIC_OFFSET_F5_3, "R200_PP_CUBIC_OFFSET_F5_3" },
   { R200_PP_TXOFFSET_4, "R200_PP_TXOFFSET_4" },
   { R200_PP_CUBIC_OFFSET_F1_4, "R200_PP_CUBIC_OFFSET_F1_4" },
   { R200_PP_CUBIC_OFFSET_F2_4, "R200_PP_CUBIC_OFFSET_F2_4" },
   { R200_PP_CUBIC_OFFSET_F3_4, "R200_PP_CUBIC_OFFSET_F3_4" },
   { R200_PP_CUBIC_OFFSET_F4_4, "R200_PP_CUBIC_OFFSET_F4_4" },
   { R200_PP_CUBIC_OFFSET_F5_4, "R200_PP_CUBIC_OFFSET_F5_4" },
   { R200_PP_TXOFFSET_5, "R200_PP_TXOFFSET_5" },
   { R200_PP_CUBIC_OFFSET_F1_5, "R200_PP_CUBIC_OFFSET_F1_5" },
   { R200_PP_CUBIC_OFFSET_F2_5, "R200_PP_CUBIC_OFFSET_F2_5" },
   { R200_PP_CUBIC_OFFSET_F3_5, "R200_PP_CUBIC_OFFSET_F3_5" },
   { R200_PP_CUBIC_OFFSET_F4_5, "R200_PP_CUBIC_OFFSET_F4_5" },
   { R200_PP_CUBIC_OFFSET_F5_5, "R200_PP_CUBIC_OFFSET_F5_5" },
   { R200_PP_TAM_DEBUG3, "R200_PP_TAM_DEBUG3" },
   { R200_PP_TFACTOR_0, "R200_PP_TFACTOR_0" },
   { R200_PP_TFACTOR_1, "R200_PP_TFACTOR_1" },
   { R200_PP_TFACTOR_2, "R200_PP_TFACTOR_2" },
   { R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" },
   { R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" },
   { R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" },
   { R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" },
   { R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" },
   { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
   { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
   { R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" },
   { R200_PP_TXABLEND2_0, "R200_PP_TXABLEND2_0" },
   { R200_PP_TXCBLEND_1, "R200_PP_TXCBLEND_1" },
   { R200_PP_TXCBLEND2_1, "R200_PP_TXCBLEND2_1" },
   { R200_PP_TXABLEND_1, "R200_PP_TXABLEND_1" },
   { R200_PP_TXABLEND2_1, "R200_PP_TXABLEND2_1" },
   { R200_PP_TXCBLEND_2, "R200_PP_TXCBLEND_2" },
   { R200_PP_TXCBLEND2_2, "R200_PP_TXCBLEND2_2" },
   { R200_PP_TXABLEND_2, "R200_PP_TXABLEND_2" },
   { R200_PP_TXABLEND2_2, "R200_PP_TXABLEND2_2" },
   { R200_PP_TXCBLEND_3, "R200_PP_TXCBLEND_3" },
   { R200_PP_TXCBLEND2_3, "R200_PP_TXCBLEND2_3" },
   { R200_PP_TXABLEND_3, "R200_PP_TXABLEND_3" },
   { R200_PP_TXABLEND2_3, "R200_PP_TXABLEND2_3" },
   { R200_PP_TXCBLEND_4, "R200_PP_TXCBLEND_4" },
   { R200_PP_TXCBLEND2_4, "R200_PP_TXCBLEND2_4" },
   { R200_PP_TXABLEND_4, "R200_PP_TXABLEND_4" },
   { R200_PP_TXABLEND2_4, "R200_PP_TXABLEND2_4" },
   { R200_PP_TXCBLEND_5, "R200_PP_TXCBLEND_5" },
   { R200_PP_TXCBLEND2_5, "R200_PP_TXCBLEND2_5" },
   { R200_PP_TXABLEND_5, "R200_PP_TXABLEND_5" },
   { R200_PP_TXABLEND2_5, "R200_PP_TXABLEND2_5" },
   { R200_PP_TXCBLEND_6, "R200_PP_TXCBLEND_6" },
   { R200_PP_TXCBLEND2_6, "R200_PP_TXCBLEND2_6" },
   { R200_PP_TXABLEND_6, "R200_PP_TXABLEND_6" },
   { R200_PP_TXABLEND2_6, "R200_PP_TXABLEND2_6" },
   { R200_PP_TXCBLEND_7, "R200_PP_TXCBLEND_7" },
   { R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" },
   { R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" },
   { R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" },
   { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" },
   { R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" },
   { R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
   { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
   { R200_PP_CNTL_X, "R200_PP_CNTL_X" },
   { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
   { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
   { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
   { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
   { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
   { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" },
   { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" },
   { R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" },
   { R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" },
   { R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" },
   { R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" },
   { R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" },
   { R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" },
   { R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" },
   { R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" },
   { R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" },
   { R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" },
   { R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" },
   { R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" },
   { R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" },
   { R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" },
   { R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" },
   { R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" },
   { R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" },
   { R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" },
   { R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" },
   { R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" },
   { R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" },
   { R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" },
   { R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" },
   { R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" },
   { R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" },
   { R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" },
   { R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" },
   { R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" },
   { R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" },
   { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" },
   { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" },
   { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" },
   { R200_VAP_PVS_CNTL_1, "R200_VAP_PVS_CNTL_1" },
   { R200_VAP_PVS_CNTL_2, "R200_VAP_PVS_CNTL_2" },
};

static struct reg_names scalar_names[] = {
   { R200_SS_LIGHT_DCD_ADDR, "R200_SS_LIGHT_DCD_ADDR" },
   { R200_SS_LIGHT_DCM_ADDR, "R200_SS_LIGHT_DCM_ADDR" },
   { R200_SS_LIGHT_SPOT_EXPONENT_ADDR, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" },
   { R200_SS_LIGHT_SPOT_CUTOFF_ADDR, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" },
   { R200_SS_LIGHT_SPECULAR_THRESH_ADDR, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" },
   { R200_SS_LIGHT_RANGE_CUTOFF_SQRD, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" },
   { R200_SS_LIGHT_RANGE_ATT_CONST, "R200_SS_LIGHT_RANGE_ATT_CONST" },
   { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" },
   { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" },
   { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" },
   { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" },
   { R200_SS_MAT_0_SHININESS, "R200_SS_MAT_0_SHININESS" },
   { R200_SS_MAT_1_SHININESS, "R200_SS_MAT_1_SHININESS" },
   { 1000, "" },
};

/* Puff these out to make them look like normal (dword) registers.
 */
static struct reg_names vector_names[] = {
   { 0, "start" },
   { R200_VS_LIGHT_AMBIENT_ADDR, "R200_VS_LIGHT_AMBIENT_ADDR" },
   { R200_VS_LIGHT_DIFFUSE_ADDR, "R200_VS_LIGHT_DIFFUSE_ADDR" },
   { R200_VS_LIGHT_SPECULAR_ADDR, "R200_VS_LIGHT_SPECULAR_ADDR" },
   { R200_VS_LIGHT_DIRPOS_ADDR, "R200_VS_LIGHT_DIRPOS_ADDR" },
   { R200_VS_LIGHT_HWVSPOT_ADDR, "R200_VS_LIGHT_HWVSPOT_ADDR" },
   { R200_VS_LIGHT_ATTENUATION_ADDR, "R200_VS_LIGHT_ATTENUATION_ADDR" },
   { R200_VS_SPOT_DUAL_CONE, "R200_VS_SPOT_DUAL_CONE" },
   { R200_VS_GLOBAL_AMBIENT_ADDR, "R200_VS_GLOBAL_AMBIENT_ADDR" },
   { R200_VS_FOG_PARAM_ADDR, "R200_VS_FOG_PARAM_ADDR" },
   { R200_VS_EYE_VECTOR_ADDR, "R200_VS_EYE_VECTOR_ADDR" },
   { R200_VS_UCP_ADDR, "R200_VS_UCP_ADDR" },
   { R200_VS_PNT_SPRITE_VPORT_SCALE, "R200_VS_PNT_SPRITE_VPORT_SCALE" },
   { R200_VS_MATRIX_0_MV, "R200_VS_MATRIX_0_MV" },
   { R200_VS_MATRIX_1_INV_MV, "R200_VS_MATRIX_1_INV_MV" },
   { R200_VS_MATRIX_2_MVP, "R200_VS_MATRIX_2_MVP" },
   { R200_VS_MATRIX_3_TEX0, "R200_VS_MATRIX_3_TEX0" },
   { R200_VS_MATRIX_4_TEX1, "R200_VS_MATRIX_4_TEX1" },
   { R200_VS_MATRIX_5_TEX2, "R200_VS_MATRIX_5_TEX2" },
   { R200_VS_MATRIX_6_TEX3, "R200_VS_MATRIX_6_TEX3" },
   { R200_VS_MATRIX_7_TEX4, "R200_VS_MATRIX_7_TEX4" },
   { R200_VS_MATRIX_8_TEX5, "R200_VS_MATRIX_8_TEX5" },
   { R200_VS_MAT_0_EMISS, "R200_VS_MAT_0_EMISS" },
   { R200_VS_MAT_0_AMB, "R200_VS_MAT_0_AMB" },
   { R200_VS_MAT_0_DIF, "R200_VS_MAT_0_DIF" },
   { R200_VS_MAT_0_SPEC, "R200_VS_MAT_0_SPEC" },
   { R200_VS_MAT_1_EMISS, "R200_VS_MAT_1_EMISS" },
   { R200_VS_MAT_1_AMB, "R200_VS_MAT_1_AMB" },
   { R200_VS_MAT_1_DIF, "R200_VS_MAT_1_DIF" },
   { R200_VS_MAT_1_SPEC, "R200_VS_MAT_1_SPEC" },
   { R200_VS_EYE2CLIP_MTX, "R200_VS_EYE2CLIP_MTX" },
   { R200_VS_PNT_SPRITE_ATT_CONST, "R200_VS_PNT_SPRITE_ATT_CONST" },
   { R200_VS_PNT_SPRITE_EYE_IN_MODEL, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" },
   { R200_VS_PNT_SPRITE_CLAMP, "R200_VS_PNT_SPRITE_CLAMP" },
   { R200_VS_MAX, "R200_VS_MAX" },
   { 1000, "" },
};

union fi { float f; int i; };

#define ISVEC   1
#define ISFLOAT 2
#define TOUCHED 4

struct reg {
   int idx; 
   struct reg_names *closest;
   int flags;
   union fi current;
   union fi *values;
   int nvalues;
   int nalloc;
   float vmin, vmax;
};


static struct reg regs[Elements(reg_names)+1];
static struct reg scalars[512+1];
static struct reg vectors[512*4+1];

static int total, total_changed, bufs;

static void init_regs( void )
{
   struct reg_names *tmp;
   int i;

   for (i = 0 ; i < Elements(regs) ; i++) {
      regs[i].idx = reg_names[i].idx;
      regs[i].closest = &reg_names[i];
      regs[i].flags = 0;
   }

   for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) {
      if (tmp[1].idx == i) tmp++;
      scalars[i].idx = i;
      scalars[i].closest = tmp;
      scalars[i].flags = ISFLOAT;
   }

   for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) {
      if (tmp[1].idx*4 == i) tmp++;
      vectors[i].idx = i;
      vectors[i].closest = tmp;
      vectors[i].flags = ISFLOAT|ISVEC;
   }

   regs[Elements(regs)-1].idx = -1;
   scalars[Elements(scalars)-1].idx = -1;
   vectors[Elements(vectors)-1].idx = -1;
}

static int find_or_add_value( struct reg *reg, int val )
{
   int j;

   for ( j = 0 ; j < reg->nvalues ; j++)
      if ( val == reg->values[j].i )
	 return 1;

   if (j == reg->nalloc) {
      reg->nalloc += 5;
      reg->nalloc *= 2;
      reg->values = (union fi *) realloc( reg->values, 
					  reg->nalloc * sizeof(union fi) );
   }

   reg->values[reg->nvalues++].i = val;
   return 0;
}

static struct reg *lookup_reg( struct reg *tab, int reg )
{
   int i;

   for (i = 0 ; tab[i].idx != -1 ; i++) {
      if (tab[i].idx == reg)
	 return &tab[i];
   }

   fprintf(stderr, "*** unknown reg 0x%x\n", reg);
   return NULL;
}


static const char *get_reg_name( struct reg *reg )
{
   static char tmp[80];

   if (reg->idx == reg->closest->idx) 
      return reg->closest->name;

   
   if (reg->flags & ISVEC) {
      if (reg->idx/4 != reg->closest->idx)
	 sprintf(tmp, "%s+%d[%d]", 
		 reg->closest->name, 
		 (reg->idx/4) - reg->closest->idx,
		 reg->idx%4);
      else
	 sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4);
   }
   else {
      if (reg->idx != reg->closest->idx)
	 sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx);
      else
	 sprintf(tmp, "%s", reg->closest->name);
   }

   return tmp;
}

static int print_int_reg_assignment( struct reg *reg, int data )
{
   int changed = (reg->current.i != data);
   int ever_seen = find_or_add_value( reg, data );
   
   if (VERBOSE || (NORMAL && (changed || !ever_seen)))
       fprintf(stderr, "   %s <-- 0x%x", get_reg_name(reg), data);
       
   if (NORMAL) {
      if (!ever_seen) 
	 fprintf(stderr, " *** BRAND NEW VALUE");
      else if (changed) 
	 fprintf(stderr, " *** CHANGED"); 
   }
   
   reg->current.i = data;

   if (VERBOSE || (NORMAL && (changed || !ever_seen)))
      fprintf(stderr, "\n");