hdllib.ref

verilog 语言去产生可以调节占空比的pwm波形 去控制信号管的开通和关断

MO pwm NULL C:/Xilinx91i/work/PWM/PWM.v vlg30/pwm.bin 1228464295
MO a NULL C:/Xilinx91i/work/PWM/a.tfw vlg61/a.bin 1228464296
MO glbl NULL C:/Xilinx91i/verilog/src/glbl.v vlg2D/glbl.bin 1228464298