timing deterministic control loops - developer zone - national instruments.mht

LabVIEW关于定时的研究的技术文档和例程

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<H1>Timing deterministic control loops</H1>
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<DIV class=3Dratings>16 =E8=AF=84=E7=BA=A7 | <STRONG>2.75</STRONG> out =
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<OL>
  <LI><A =
href=3D"http://zone.ni.com/devzone/cda/tut/p/id/4324#toc0">Overview</A>
  <LI><A =
href=3D"http://zone.ni.com/devzone/cda/tut/p/id/4324#toc1">Using =
Software=20
  to time control loops</A>
  <LI><A =
href=3D"http://zone.ni.com/devzone/cda/tut/p/id/4324#toc2">Anchoring =
loop=20
  times to hardware clock</A>
  <LI><A =
href=3D"http://zone.ni.com/devzone/cda/tut/p/id/4324#toc3">Synchronizing =

  input and output clocks</A>
  <LI><A =
href=3D"http://zone.ni.com/devzone/cda/tut/p/id/4324#toc4">Staggering=20
  input and output clocks</A></LI></OL></DIV><A name=3Dtoc0></A>
<H2>Overview</H2>
<P>One of the major factors of a control system is response time. In =
general, a=20
control loop cyclically acquires a single point from an input channel, =
processes=20
it, and in response, outputs a single point on an output channel. =
Control loops=20
simply repeat this process. Although a computer=E2=80=99s processor =
speed and the number=20
of instructions inside the control loop generally limit the maximum =
frequency of=20
a control loop, a programmer has some flexibility when tuning a control =
loop=E2=80=99s=20
responsiveness between inputs and outputs. Consider the following =
figure, which=20
illustrates a simple timeline of inputs and outputs for a software-timed =

acquisition.<BR></P>
<P><IMG height=3D108 alt=3D""=20
src=3D"http://zone.ni.com/cms/images/devzone/tut/timing_deterministic_con=
trol_loops.gif"=20
width=3D396 border=3D0></P>
<P>The minimum time between input and output depends on the amount of =
processing=20
that must be done on each input. Thus we must guarantee that the output =
command=20
occurs only after the processing is complete. The overall loop cycle =
time is=20
simply the sum of the processing time and any built-in delay.<BR></P><A=20
name=3Dtoc1></A>
<H2>Using Software to time control loops</A><BR></H2>The easiest way to =
time a=20
control loop is to use software tools to wake up the software thread at =
regular=20
intervals. One such tool is the "Wait Until Next ms Multiple" VI. =
<BR><BR><IMG=20
height=3D118 alt=3D""=20
src=3D"http://zone.ni.com/cms/images/devzone/tut/a/5b519f241037.gif"=20
width=3D242><BR><BR>One disadvantage, of course, is the millisecond =
resolution of=20
the function, which limits you to 1 kHz loop rates maximum. In the =
software=20
timing scheme, all three components - input, processing, and output, are =
subject=20
to software jitter.<BR><BR><A=20
onclick=3D"window.open('http://zone.ni.com/devzone/jsp/largeImage.jsp?ima=
gename=3D/cms/images/devzone/tut/a/5b519f241038.gif&amp;language=3Dzh-CN'=
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,'awindow','scrollbars=3Dyes,resizable=3Dyes');return false;"=20
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=E6=94=BE=E5=A4=A7=E5=9B=BE=E7=89=87</A> <A name=3Dtoc2></A>
<H2>Anchoring loop times to hardware clock</A><BR></H2><BR>In order to =
achieve=20
faster loop rates, and to remove some of the software jitter from our =
loop, it=20
is desirable to examine some hardware timing solutions.<BR><BR>Starting =
with=20
NI-DAQ 6.7, AI SingleScan anchors a thread in software to the =
board=E2=80=99s hardware=20
scanclock. Thus the scan rate defines the frequency of the loop. With =
this=20
method, we can achieve loop rates much faster than 1 kHz as long as the =
code=20
inside the control loop does not lag the scanning process. When AI =
SingleScan is=20
called, it waits for the next rising edge of the scanclock before it =
executes.=20
While it waits, it puts to sleep the calling time-critical thread, so =
other=20
lower-priority threads can execute.<BR><BR>It also is possible to use an =
E=20
Series STC counter to time control loops by adding the "Wait" operation. =
<A=20
name=3Dtoc3></A>
<H2>Synchronizing input and output clocks</A><BR></H2><BR>An easy way to =
ensure=20
that there is a regular delay between the input and output events is to =
perform=20
inputs and outputs at the same time. You can do this by simply sharing a =
common=20
clock for A/D and D/A conversions to ensure that both occur =
synchronously. In=20
the case of National Instruments Data Acquisition boards, a shared clock =
can be=20
the output of a counter routed over RTSI to both the update and scan =
clocks, the=20
scan clock routed to the update clock, the update clock routed to the =
scan=20
clock, etc. The drawback, however, is that outputs are always one loop =
cycle=20
behind the inputs. Refer to the following figure for more information =
about the=20
delay.<BR><BR><IMG height=3D156 alt=3D""=20
src=3D"http://zone.ni.com/cms/images/devzone/tut/a/5b519f241039.gif"=20
width=3D444><BR><BR>Analog input and output are now synchronized. The =
time delay=20
between them is exact and predictable, and subject only to the hardware =
jitter=20
of our scan clock, which is in the order of nanoseconds. <A =
name=3Dtoc4></A>
<H2>Staggering input and output clocks</A><BR></H2><BR>To minimize the =
time=20
between an input and its corresponding output, you might consider =
staggering the=20
scan clock (A/D) and update clock (D/A) as shown in the first figure. In =
this=20
implementation, the output occurs as soon as the processing is complete. =
In=20
other words, the software dictates the timing of our output. However, we =
cannot=20
implement software timing and expect the delay between the input and =
output=20
events to be regular. To do that, we need to use hardware timing and =
thus a=20
clock to guarantee that inputs and outputs occur at regular intervals =
with=20
minimal jitter. Using one clock, we can stagger A/D and D/A conversions =
by=20
initiating an input on the rising edge of our clock and initiating an =
output on=20
the falling edge of the same clock. Adjusting the clock=E2=80=99s duty =
cycle enables us=20
to vary the time between inputs and outputs until we have optimized the =
loop=20
cycle time. In addition, in some cases, we can divide the processing =
routine=20
into =E2=80=9Cpre-processing=E2=80=9D and =
=E2=80=9Cpost-processing=E2=80=9D sections. Dividing the processing=20
routine establishes an even smaller response time between inputs and =
outputs by=20
shifting some of the processing elsewhere as shown in the following=20
figure.<BR><BR><A=20
onclick=3D"window.open('http://zone.ni.com/devzone/jsp/largeImage.jsp?ima=
gename=3D/cms/images/devzone/tut/a/5b519f241040.gif&amp;language=3Dzh-CN'=
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href=3D"http://zone.ni.com/devzone/cda/tut/p/id/">[+] =
=E6=94=BE=E5=A4=A7=E5=9B=BE=E7=89=87</A> <BR><B>Related=20
Links:</B><BR><A =
href=3D"http://zone.ni.com/devzone/cda/epd/p/id/3259">Staggering=20
the Scan Clock and Update Clock</A><BR>
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