myfx2.hier_info

用于USB20芯片CY7C68013和FPGA之间的通信

|MYFX2
nRESET => Mega_cnt[22].ACLR
nRESET => Mega_cnt[21].ACLR
nRESET => Mega_cnt[20].ACLR
nRESET => Mega_cnt[19].ACLR
nRESET => Mega_cnt[18].ACLR
nRESET => Mega_cnt[17].ACLR
nRESET => Mega_cnt[16].ACLR
nRESET => Mega_cnt[15].ACLR
nRESET => Mega_cnt[14].ACLR
nRESET => Mega_cnt[13].ACLR
nRESET => Mega_cnt[12].ACLR
nRESET => Mega_cnt[11].ACLR
nRESET => Mega_cnt[10].ACLR
nRESET => Mega_cnt[9].ACLR
nRESET => Mega_cnt[8].ACLR
nRESET => Mega_cnt[7].ACLR
nRESET => Mega_cnt[6].ACLR
nRESET => Mega_cnt[5].ACLR
nRESET => Mega_cnt[4].ACLR
nRESET => Mega_cnt[3].ACLR
nRESET => Mega_cnt[2].ACLR
nRESET => Mega_cnt[1].ACLR
nRESET => Mega_cnt[0].ACLR
nRESET => Mega_cnt[23].ACLR
nRESET => LDT.ENA
PA[0] => LED[0].DATAIN
PA[1] => LED[1].DATAIN
PA[2] => LED[2].DATAIN
PA[3] => ~NO_FANOUT~
PA[4] => ~NO_FANOUT~
PA[5] => ~NO_FANOUT~
PA[6] => ~NO_FANOUT~
PA[7] => ~NO_FANOUT~
GPD[0] <= KEY[0]
GPD[1] <= KEY[1]
GPD[2] <= KEY[2]
GPD[3] <= <UNC>
GPD[4] <= <UNC>
GPD[5] <= <UNC>
GPD[6] <= <UNC>
GPD[7] <= <UNC>
GPD[8] <= <UNC>
GPD[9] <= <UNC>
GPD[10] <= <UNC>
GPD[11] <= <UNC>
GPD[12] <= <UNC>
GPD[13] <= <UNC>
GPD[14] <= <UNC>
GPD[15] <= <UNC>
GPA[0] => ~NO_FANOUT~
GPA[1] => ~NO_FANOUT~
GPA[2] => ~NO_FANOUT~
GPA[3] => ~NO_FANOUT~
GPA[4] => ~NO_FANOUT~
GPA[5] => ~NO_FANOUT~
GPA[6] => ~NO_FANOUT~
GPA[7] => ~NO_FANOUT~
GPA[8] => ~NO_FANOUT~
CTL[0] => ~NO_FANOUT~
CTL[1] => ~NO_FANOUT~
CTL[2] => ~NO_FANOUT~
CTL[3] => ~NO_FANOUT~
CTL[4] => ~NO_FANOUT~
CTL[5] => ~NO_FANOUT~
RDY[0] => ~NO_FANOUT~
RDY[1] => ~NO_FANOUT~
RDY[2] => ~NO_FANOUT~
RDY[3] => ~NO_FANOUT~
RDY[4] => ~NO_FANOUT~
RDY[5] => ~NO_FANOUT~
USER[0] => ~NO_FANOUT~
USER[1] => ~NO_FANOUT~
USER[2] => ~NO_FANOUT~
USER[3] => ~NO_FANOUT~
USER[4] => ~NO_FANOUT~
USER[5] => ~NO_FANOUT~
IFCLK => ~NO_FANOUT~
CLKOUT => ~NO_FANOUT~
nINT5 => ~NO_FANOUT~
MMCLK => Mega_cnt[22].CLK
MMCLK => Mega_cnt[21].CLK
MMCLK => Mega_cnt[20].CLK
MMCLK => Mega_cnt[19].CLK
MMCLK => Mega_cnt[18].CLK
MMCLK => Mega_cnt[17].CLK
MMCLK => Mega_cnt[16].CLK
MMCLK => Mega_cnt[15].CLK
MMCLK => Mega_cnt[14].CLK
MMCLK => Mega_cnt[13].CLK
MMCLK => Mega_cnt[12].CLK
MMCLK => Mega_cnt[11].CLK
MMCLK => Mega_cnt[10].CLK
MMCLK => Mega_cnt[9].CLK
MMCLK => Mega_cnt[8].CLK
MMCLK => Mega_cnt[7].CLK
MMCLK => Mega_cnt[6].CLK
MMCLK => Mega_cnt[5].CLK
MMCLK => Mega_cnt[4].CLK
MMCLK => Mega_cnt[3].CLK
MMCLK => Mega_cnt[2].CLK
MMCLK => Mega_cnt[1].CLK
MMCLK => Mega_cnt[0].CLK
MMCLK => Mega_cnt[23].CLK
LED[0] <= PA[0].DB_MAX_OUTPUT_PORT_TYPE
LED[1] <= PA[1].DB_MAX_OUTPUT_PORT_TYPE
LED[2] <= PA[2].DB_MAX_OUTPUT_PORT_TYPE
LED[3] <= LDT.DB_MAX_OUTPUT_PORT_TYPE
KEY[0] => KEY[0]~2.IN1
KEY[1] => KEY[1]~1.IN1
KEY[2] => KEY[2]~0.IN1
RAMAA[0] <= <GND>
RAMAA[1] <= <GND>
RAMAA[2] <= <GND>
RAMAA[3] <= <GND>
RAMAA[4] <= <GND>
RAMAA[5] <= <GND>
RAMAA[6] <= <GND>
RAMAA[7] <= <GND>
RAMAA[8] <= <GND>
RAMAA[9] <= <GND>
RAMAA[10] <= <GND>
RAMAA[11] <= <GND>
RAMAA[12] <= <GND>
RAMAA[13] <= <GND>
RAMAA[14] <= <GND>
RAMAA[15] <= <GND>
RAMAA[16] <= <GND>
RAMAA[17] <= <GND>
RAMAD[0] <= <UNC>
RAMAD[1] <= <UNC>
RAMAD[2] <= <UNC>
RAMAD[3] <= <UNC>
RAMAD[4] <= <UNC>
RAMAD[5] <= <UNC>
RAMAD[6] <= <UNC>
RAMAD[7] <= <UNC>
RAMAD[8] <= <UNC>
RAMAD[9] <= <UNC>
RAMAD[10] <= <UNC>
RAMAD[11] <= <UNC>
RAMAD[12] <= <UNC>
RAMAD[13] <= <UNC>
RAMAD[14] <= <UNC>
RAMAD[15] <= <UNC>
RAMAUB <= <GND>
RAMALB <= <GND>
RAMAWE <= <GND>
RAMACE <= <GND>
RAMAOE <= <GND>
RAMBA[0] <= <GND>
RAMBA[1] <= <GND>
RAMBA[2] <= <GND>
RAMBA[3] <= <GND>
RAMBA[4] <= <GND>
RAMBA[5] <= <GND>
RAMBA[6] <= <GND>
RAMBA[7] <= <GND>
RAMBA[8] <= <GND>
RAMBA[9] <= <GND>
RAMBA[10] <= <GND>
RAMBA[11] <= <GND>
RAMBA[12] <= <GND>
RAMBA[13] <= <GND>
RAMBA[14] <= <GND>
RAMBA[15] <= <GND>
RAMBA[16] <= <GND>
RAMBA[17] <= <GND>
RAMBD[0] <= <UNC>
RAMBD[1] <= <UNC>
RAMBD[2] <= <UNC>
RAMBD[3] <= <UNC>
RAMBD[4] <= <UNC>
RAMBD[5] <= <UNC>
RAMBD[6] <= <UNC>
RAMBD[7] <= <UNC>
RAMBD[8] <= <UNC>
RAMBD[9] <= <UNC>
RAMBD[10] <= <UNC>
RAMBD[11] <= <UNC>
RAMBD[12] <= <UNC>
RAMBD[13] <= <UNC>
RAMBD[14] <= <UNC>
RAMBD[15] <= <UNC>
RAMBUB <= <GND>
RAMBLB <= <GND>
RAMBWE <= <GND>
RAMBCE <= <GND>
RAMBOE <= <GND>