myfx2.map.qmsg

用于USB20芯片CY7C68013和FPGA之间的通信

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 06 19:48:32 2007 " "Info: Processing started: Tue Feb 06 19:48:32 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MYFX2 -c MYFX2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MYFX2 -c MYFX2" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MYFX2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MYFX2.v" { { "Info" "ISGN_ENTITY_NAME" "1 MYFX2 " "Info: Found entity 1: MYFX2" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "MYFX2 " "Info: Elaborating entity \"MYFX2\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 MYFX2.v(59) " "Warning: Verilog HDL assignment warning at MYFX2.v(59): truncated value with size 32 to match size of target (24)" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 MYFX2.v(63) " "Warning: Verilog HDL assignment warning at MYFX2.v(63): truncated value with size 32 to match size of target (24)" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 MYFX2.v(76) " "Warning: Verilog HDL assignment warning at MYFX2.v(76): truncated value with size 32 to match size of target (1)" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 76 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dir MYFX2.v(71) " "Warning: Verilog HDL Always Construct warning at MYFX2.v(71): variable \"dir\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"dir\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 71 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[17\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[17\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[16\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[16\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[15\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[15\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[14\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[14\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[13\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[13\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[12\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[12\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[11\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[11\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}