📄 myfx2.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[7\] " "Info: Node \"DREG\[7\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[6\] " "Info: Node \"DREG\[6\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[5\] " "Info: Node \"DREG\[5\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[4\] " "Info: Node \"DREG\[4\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[3\] " "Info: Node \"DREG\[3\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[2\] " "Info: Node \"DREG\[2\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[1\] " "Info: Node \"DREG\[1\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[0\] " "Info: Node \"DREG\[0\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CTL\[5\] GPD\[12\] 16.239 ns Longest " "Info: Longest tpd from source pin \"CTL\[5\]\" to destination pin \"GPD\[12\]\" is 16.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CTL\[5\] 1 PIN PIN_20 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_20; Fanout = 34; PIN Node = 'CTL\[5\]'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/" "" "" { CTL[5] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.006 ns) + CELL(0.114 ns) 8.589 ns DREG~72 2 COMB LC_X6_Y1_N0 32 " "Info: 2: + IC(7.006 ns) + CELL(0.114 ns) = 8.589 ns; Loc. = LC_X6_Y1_N0; Fanout = 32; COMB Node = 'DREG~72'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/" "" "7.120 ns" { CTL[5] DREG~72 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.746 ns) 10.335 ns DREG\[12\] 3 COMB LOOP LC_X7_Y2_N4 3 " "Info: 3: + IC(0.000 ns) + CELL(1.746 ns) = 10.335 ns; Loc. = LC_X7_Y2_N4; Fanout = 3; COMB LOOP Node = 'DREG\[12\]'" { { "Info" "ITDB_PART_OF_SCC" "DREG\[12\] LC_X7_Y2_N4 " "Info: Loc. = LC_X7_Y2_N4; Node \"DREG\[12\]\"" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/" "" "" { DREG[12] } "NODE_NAME" } "" } } } 0} } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/" "" "" { DREG[12] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/" "" "1.746 ns" { DREG~72 DREG[12] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.780 ns) + CELL(2.124 ns) 16.239 ns GPD\[12\] 4 PIN PIN_4 0 " "Info: 4: + IC(3.780 ns) + CELL(2.124 ns) = 16.239 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'GPD\[12\]'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/" "" "5.904 ns" { DREG[12] GPD[12] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.453 ns 33.58 % " "Info: Total cell delay = 5.453 ns ( 33.58 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.786 ns 66.42 % " "Info: Total interconnect delay = 10.786 ns ( 66.42 % )" { } { } 0} } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/" "" "16.239 ns" { CTL[5] DREG~72 DREG[12] GPD[12] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.239 ns" { CTL[5] CTL[5]~out0 DREG~72 DREG[12] GPD[12] } { 0.000ns 0.000ns 7.006ns 0.000ns 3.780ns } { 0.000ns 1.469ns 0.114ns 1.746ns 2.124ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 17 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 06 19:41:52 2007 " "Info: Processing ended: Tue Feb 06 19:41:52 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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