myfx2.tan.qmsg

用于USB20芯片CY7C68013和FPGA之间的通信

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 06 19:41:51 2007 " "Info: Processing started: Tue Feb 06 19:41:51 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off MYFX2 -c MYFX2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MYFX2 -c MYFX2 --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[0\] " "Warning: Node \"DREG\[0\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[1\] " "Warning: Node \"DREG\[1\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[2\] " "Warning: Node \"DREG\[2\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[3\] " "Warning: Node \"DREG\[3\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[4\] " "Warning: Node \"DREG\[4\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[5\] " "Warning: Node \"DREG\[5\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[6\] " "Warning: Node \"DREG\[6\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[7\] " "Warning: Node \"DREG\[7\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[8\] " "Warning: Node \"DREG\[8\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[9\] " "Warning: Node \"DREG\[9\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[10\] " "Warning: Node \"DREG\[10\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[11\] " "Warning: Node \"DREG\[11\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[12\] " "Warning: Node \"DREG\[12\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[13\] " "Warning: Node \"DREG\[13\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[14\] " "Warning: Node \"DREG\[14\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DREG\[15\] " "Warning: Node \"DREG\[15\]\" is a latch" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[15\] " "Info: Node \"DREG\[15\]\"" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[14\] " "Info: Node \"DREG\[14\]\"" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[13\] " "Info: Node \"DREG\[13\]\"" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[12\] " "Info: Node \"DREG\[12\]\"" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[11\] " "Info: Node \"DREG\[11\]\"" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[10\] " "Info: Node \"DREG\[10\]\"" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[9\] " "Info: Node \"DREG\[9\]\"" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DREG\[8\] " "Info: Node \"DREG\[8\]\"" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}