📄 myfx2.map.qmsg
字号:
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[5\] " "Warning: Latch DREG\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[6\] " "Warning: Latch DREG\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[7\] " "Warning: Latch DREG\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[8\] " "Warning: Latch DREG\[8\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[9\] " "Warning: Latch DREG\[9\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[10\] " "Warning: Latch DREG\[10\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[11\] " "Warning: Latch DREG\[11\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[12\] " "Warning: Latch DREG\[12\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[13\] " "Warning: Latch DREG\[13\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[14\] " "Warning: Latch DREG\[14\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[15\] " "Warning: Latch DREG\[15\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } } } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[0\] GND " "Warning: Pin \"LED\[0\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 36 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[1\] GND " "Warning: Pin \"LED\[1\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 36 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[2\] GND " "Warning: Pin \"LED\[2\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 36 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[3\] GND " "Warning: Pin \"LED\[3\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 36 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[0\] GND " "Warning: Pin \"RAMAA\[0\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[1\] GND " "Warning: Pin \"RAMAA\[1\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[2\] GND " "Warning: Pin \"RAMAA\[2\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[3\] GND " "Warning: Pin \"RAMAA\[3\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[4\] GND " "Warning: Pin \"RAMAA\[4\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[5\] GND " "Warning: Pin \"RAMAA\[5\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[6\] GND " "Warning: Pin \"RAMAA\[6\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[7\] GND " "Warning: Pin \"RAMAA\[7\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[8\] GND " "Warning: Pin \"RAMAA\[8\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[9\] GND " "Warning: Pin \"RAMAA\[9\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[10\] GND " "Warning: Pin \"RAMAA\[10\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[11\] GND " "Warning: Pin \"RAMAA\[11\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[12\] GND " "Warning: Pin \"RAMAA\[12\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[13\] GND " "Warning: Pin \"RAMAA\[13\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[14\] GND " "Warning: Pin \"RAMAA\[14\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[15\] GND " "Warning: Pin \"RAMAA\[15\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[16\] GND " "Warning: Pin \"RAMAA\[16\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAA\[17\] GND " "Warning: Pin \"RAMAA\[17\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAUB GND " "Warning: Pin \"RAMAUB\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMALB GND " "Warning: Pin \"RAMALB\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAWE GND " "Warning: Pin \"RAMAWE\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMACE GND " "Warning: Pin \"RAMACE\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMAOE GND " "Warning: Pin \"RAMAOE\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMBA\[15\] GND " "Warning: Pin \"RAMBA\[15\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 14 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMBA\[16\] GND " "Warning: Pin \"RAMBA\[16\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 14 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMBA\[17\] GND " "Warning: Pin \"RAMBA\[17\]\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 14 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMBUB VCC " "Warning: Pin \"RAMBUB\" stuck at VCC" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 19 -1 0 } } } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RAMBLB GND " "Warning: Pin \"RAMBLB\" stuck at GND" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 19 -1 0 } } } 0} } { } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "25 " "Warning: Design contains 25 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "nRESET " "Warning: No output dependent on input pin \"nRESET\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 21 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "PA\[6\] " "Warning: No output dependent on input pin \"PA\[6\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 23 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "PA\[7\] " "Warning: No output dependent on input pin \"PA\[7\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 23 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CTL\[0\] " "Warning: No output dependent on input pin \"CTL\[0\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CTL\[1\] " "Warning: No output dependent on input pin \"CTL\[1\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CTL\[2\] " "Warning: No output dependent on input pin \"CTL\[2\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RDY\[0\] " "Warning: No output dependent on input pin \"RDY\[0\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 28 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RDY\[1\] " "Warning: No output dependent on input pin \"RDY\[1\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 28 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RDY\[2\] " "Warning: No output dependent on input pin \"RDY\[2\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 28 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RDY\[3\] " "Warning: No output dependent on input pin \"RDY\[3\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 28 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RDY\[4\] " "Warning: No output dependent on input pin \"RDY\[4\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 28 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RDY\[5\] " "Warning: No output dependent on input pin \"RDY\[5\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 28 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "USER\[0\] " "Warning: No output dependent on input pin \"USER\[0\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 29 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "USER\[1\] " "Warning: No output dependent on input pin \"USER\[1\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 29 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "USER\[2\] " "Warning: No output dependent on input pin \"USER\[2\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 29 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "USER\[3\] " "Warning: No output dependent on input pin \"USER\[3\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 29 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "USER\[4\] " "Warning: No output dependent on input pin \"USER\[4\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 29 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "USER\[5\] " "Warning: No output dependent on input pin \"USER\[5\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 29 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "IFCLK " "Warning: No output dependent on input pin \"IFCLK\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 30 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CLKOUT " "Warning: No output dependent on input pin \"CLKOUT\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 30 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "nINT5 " "Warning: No output dependent on input pin \"nINT5\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 30 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "MMCLK " "Warning: No output dependent on input pin \"MMCLK\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 33 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "Warning: No output dependent on input pin \"KEY\[0\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 34 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning: No output dependent on input pin \"KEY\[1\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 34 -1 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "Warning: No output dependent on input pin \"KEY\[2\]\"" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 34 -1 0 } } } 0} } { } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "174 " "Info: Implemented 174 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "43 " "Info: Implemented 43 input pins" { } { } 0} { "Info" "ISCL_SCL_TM_OPINS" "50 " "Info: Implemented 50 output pins" { } { } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "48 " "Info: Implemented 48 bidirectional pins" { } { } 0} { "Info" "ISCL_SCL_TM_LCELLS" "33 " "Info: Implemented 33 logic cells" { } { } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 131 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 131 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 06 19:41:24 2007 " "Info: Processing ended: Tue Feb 06 19:41:24 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0} } { } 0}
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