myfx2.map.qmsg

用于USB20芯片CY7C68013和FPGA之间的通信

{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[2\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[2\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[1\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[1\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[0\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[0\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAUB MYFX2.v(18) " "Warning: Output port \"RAMAUB\" at MYFX2.v(18) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMALB MYFX2.v(18) " "Warning: Output port \"RAMALB\" at MYFX2.v(18) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAWE MYFX2.v(18) " "Warning: Output port \"RAMAWE\" at MYFX2.v(18) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMACE MYFX2.v(18) " "Warning: Output port \"RAMACE\" at MYFX2.v(18) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAOE MYFX2.v(18) " "Warning: Output port \"RAMAOE\" at MYFX2.v(18) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LED\[3\] MYFX2.v(36) " "Warning: Output port \"LED\[3\]\" at MYFX2.v(36) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LED\[2\] MYFX2.v(36) " "Warning: Output port \"LED\[2\]\" at MYFX2.v(36) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LED\[1\] MYFX2.v(36) " "Warning: Output port \"LED\[1\]\" at MYFX2.v(36) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LED\[0\] MYFX2.v(36) " "Warning: Output port \"LED\[0\]\" at MYFX2.v(36) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 36 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[0\] " "Warning: Latch DREG\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[1\] " "Warning: Latch DREG\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[2\] " "Warning: Latch DREG\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[3\] " "Warning: Latch DREG\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DREG\[4\] " "Warning: Latch DREG\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CTL\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal CTL\[5\]" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 27 -1 0 } }  } 0}  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 32 -1 0 } }  } 0}