myfx2.map.qmsg

用于USB20芯片CY7C68013和FPGA之间的通信

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 MYFX2.v(84) " "Warning: Verilog HDL assignment warning at MYFX2.v(84): truncated value with size 32 to match size of target (1)" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 MYFX2.v(85) " "Warning: Verilog HDL assignment warning at MYFX2.v(85): truncated value with size 32 to match size of target (1)" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[17\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[17\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[16\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[16\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[15\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[15\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[14\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[14\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[13\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[13\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[12\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[12\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[11\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[11\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[10\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[10\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[9\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[9\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[8\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[8\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[7\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[7\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[6\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[6\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[5\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[5\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[4\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[4\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "RAMAA\[3\] MYFX2.v(13) " "Warning: Output port \"RAMAA\[3\]\" at MYFX2.v(13) has no driver" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_GPIF_RW_SRAM测试/FPGA代码/MYFX2.v" 13 0 0 } }  } 0}