myfx2.tan.qmsg

用于USB20芯片CY7C68013和FPGA之间的通信

{ "Info" "ITDB_FULL_TCO_RESULT" "MMCLK GPD\[5\] RDY\[1\]~reg0 16.410 ns register " "Info: tco from clock \"MMCLK\" to destination pin \"GPD\[5\]\" through register \"RDY\[1\]~reg0\" is 16.410 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK source 10.766 ns + Longest register " "Info: + Longest clock path from clock \"MMCLK\" to source register is 10.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'MMCLK'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.358 ns) + CELL(0.935 ns) 5.762 ns CLK_2 2 REG LC_X3_Y14_N2 2 " "Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N2; Fanout = 2; REG Node = 'CLK_2'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "4.293 ns" { MMCLK CLK_2 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 7.264 ns CLK_4 3 REG LC_X3_Y14_N4 2 " "Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 7.264 ns; Loc. = LC_X3_Y14_N4; Fanout = 2; REG Node = 'CLK_4'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "1.502 ns" { CLK_2 CLK_4 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.285 ns) + CELL(0.935 ns) 9.484 ns CLK_8 4 REG LC_X3_Y15_N6 20 " "Info: 4: + IC(1.285 ns) + CELL(0.935 ns) = 9.484 ns; Loc. = LC_X3_Y15_N6; Fanout = 20; REG Node = 'CLK_8'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "2.220 ns" { CLK_4 CLK_8 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.711 ns) 10.766 ns RDY\[1\]~reg0 5 REG LC_X3_Y15_N5 18 " "Info: 5: + IC(0.571 ns) + CELL(0.711 ns) = 10.766 ns; Loc. = LC_X3_Y15_N5; Fanout = 18; REG Node = 'RDY\[1\]~reg0'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "1.282 ns" { CLK_8 RDY[1]~reg0 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 108 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.985 ns 46.30 % " "Info: Total cell delay = 4.985 ns ( 46.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.781 ns 53.70 % " "Info: Total interconnect delay = 5.781 ns ( 53.70 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "10.766 ns" { MMCLK CLK_2 CLK_4 CLK_8 RDY[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.766 ns" { MMCLK MMCLK~out0 CLK_2 CLK_4 CLK_8 RDY[1]~reg0 } { 0.000ns 0.000ns 3.358ns 0.567ns 1.285ns 0.571ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 108 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.420 ns + Longest register pin " "Info: + Longest register to pin delay is 5.420 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RDY\[1\]~reg0 1 REG LC_X3_Y15_N5 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y15_N5; Fanout = 18; REG Node = 'RDY\[1\]~reg0'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "" { RDY[1]~reg0 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 108 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.341 ns) + CELL(2.079 ns) 5.420 ns GPD\[5\] 2 PIN PIN_62 0 " "Info: 2: + IC(3.341 ns) + CELL(2.079 ns) = 5.420 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'GPD\[5\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "5.420 ns" { RDY[1]~reg0 GPD[5] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.079 ns 38.36 % " "Info: Total cell delay = 2.079 ns ( 38.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.341 ns 61.64 % " "Info: Total interconnect delay = 3.341 ns ( 61.64 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "5.420 ns" { RDY[1]~reg0 GPD[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.420 ns" { RDY[1]~reg0 GPD[5] } { 0.000ns 3.341ns } { 0.000ns 2.079ns } } }  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "10.766 ns" { MMCLK CLK_2 CLK_4 CLK_8 RDY[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.766 ns" { MMCLK MMCLK~out0 CLK_2 CLK_4 CLK_8 RDY[1]~reg0 } { 0.000ns 0.000ns 3.358ns 0.567ns 1.285ns 0.571ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "5.420 ns" { RDY[1]~reg0 GPD[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.420 ns" { RDY[1]~reg0 GPD[5] } { 0.000ns 3.341ns } { 0.000ns 2.079ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 06 20:43:52 2007 " "Info: Processing ended: Tue Feb 06 20:43:52 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}